Pyramancer
Fairly Idle Member
- Joined
- Feb 4, 2017
- Messages
- 232
- Age
- 125
If that's so, then it could at least help in narrowing down the cause(s) of the 4 GB issue.Why not use 3GB of it? That's the limit without LPAE right?
If that's so, then it could at least help in narrowing down the cause(s) of the 4 GB issue.Why not use 3GB of it? That's the limit without LPAE right?
@hns that means the pyra can run stable in 2GB mode, even when there is a 4gb chip soldered on it?
So far we have no indication of the opposite.
[joining your sarcasm]Did someone just mention 8GB?
The 4GB memory chips work fine in standard 2GB software mode on all prototype CPU boards I have tested so far.
Only trying to make 4GB available in U-Boot (different EMIF config) and use it in kernel (LPAE enabled) raises issues in kernel.
The kernel boots, shows 4GB being available but runs instable.
Which might either be
- pure software (imprecise memory controller config, wrong virtual memory management, wrong cache management) or
- hardware (more noise, more power demand, more whatever, as soon as the second bank inside the 4GB chip becomes active).
Further tests to find out are planned but not yet done.
So turning 4GB off and using 2GB is just using the standard 2GB U-Boot and Kernel. No need for a hw switch.
Blue cases are as wrong as blue teeth.
IMO
haha, don't be silly... it is a πra... so it should be 3.14159 cm thick...Is the Pyra still 3.2cm thick? It looks thicker in the Video.
Agreed. When I first saw those images I thought he might have cracked displays during assembly. It took closer inspection to realize it's just the peel-away shipping & assembly scratch guard layer.I so want to rip the foil off those displays…
Does anyone else sometimes leave that on for a bit?
you guys are psychoSometime, until I get a screen protector.