netlinker
Active Member
OMAP+TWL6040 use a protocol called McPDM but it is similar to SPI and I2S. Unfortunately we have not found any registers for inverting the clock out pin... If you are interested in the details, it is twl6040 erratum #8 "PDM Downlink Data Corrupted" in TI document SWCZ0007D from 2011 (it seems to be NDA only).
I couldn't find any technical reference manual for the OMAP 5, but if a Sitara am572x is close enough, I might have a solution. In the Sitara manual:
there is a paragraph about the Audio Interface called McASP in this case that references to the Paragraph 18.4.6.1 Pad configuration. There you have several registers setting the IO timing (Virtual timing mode) as well as the pull strength of the corresponding pin.
If you check out 18.4.6.1 and following there is a detailed description about calibration of IO timing. As the Pad configuration seems to be function independent and functional for each individual pin, this might be a solution if existent on the OMAP.
They also state that this IO timing recalibration should be done on every core domain voltage change, if I understood correctly.
None technical people have been warned, the document has 8000 Pages .