The joys of hardware design. ED pretty much jinxed this from the start with the overconfidence he showed about it, I was just waiting for a mistake in the layout to show its ugly face
I was expecting a mistake or more, but was hoping it was one that doesn't prevent testing the rest!
I actualy expected much more errors with that complex 10 layer board. Especialy when it was designed basicly by hand and by one person. So if there is only one mistake, it's already very impressive.
But to be realistic, there may be much more issues coming up that need some redesign. No hardware works perfect with it's first prototype.
Indeed. This is why prototypes (usually several generations) are needed. For the main board of the Pyra we currently have the fourth and the fifth is planned to go to mass production. So we would have been very lucky if the first CPU board would have been 100% perfect.
But PCB layout is almost always done by one person. It can rarely be split and parallelized (well, multiple PCBs can - if the positions of connectors and pin assignments are negotiated). The trick is to have EDA tools that do design rule checks (e.g. minimum distance between chips, wire traces etc.) while doing the hard manual work. This avoids most of the simple errors. The question is if this can be still recognized as being done "by hand"... In my experience auto-routers are not useable for such complex boards. They are good for very simple projects.
What no tool can avoid is a mistake introduced when translating printed data sheets into the EDA tool. This is very comparable to retyping a text from a printed textbook into a different word processor. Typos happen. And are unavoidable and pass unnoticed by the person who types, even if careful. They also become visible only if a first proof is printed and someone looks on it and sees the typo. And unfortunately predefined component libraries are not available for everything and in all data formats.
In fact we have another such translation bug - but it is not a visible problem since it does not affect the copper wires. The component placement printing for the DRAMs is shifted by 0.4mm. So the chips do look still misplaced, even if placed correctly. And because of the same problem they were misplaced initially and we have got them (almost) repaired now.
Another potential problem is that wrong settings of the design rules can make a layout unuseable. If rules are not correctly strict, the layout designer can do wrong things without notice. But for this, the PCB manufacturer does his own tests so that such errors don't pass the production entry guard. But the PCB manufacturer can not check for logical errors as described before.