The Pyra Puzzle


those type of connector for board interconnects are quite firm. i dont think they could come loose without some significant force which would surely entail damage to the case and other parts of the Pyra. besides there isn't a lot of room above the CPU board for it to  go anywhere.
 
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Inside of that picture are at least 3 major and 8 small rule infringements. If we keep it like that, the PCB could not be produced reliably, would get shortcircuits or similar issues.

Moving traces around could lead to other rule infringements - so this is quite a puzzle (high-level Sokoban, eh?)

Each issue needs about 5 - 30 minutes to solve, so it's possible, just takes a loooot of time.

And the more you solve, the more complicated it gets for the remaining ones... fun.
 But how can he be sure that there is an existing solution?
sometimes there is not a solution without a complete redesign of the board layout. some packages can auto route for you but on complicated boards may still only do 95% if you are lucky. the remaining 5% is where the art come in.. loltraces on multi layer boards can be fed through a 3 dimensional maze up and down layers as well as across layers. but those sorts of traces can give other problems with noise and crosstalk of signals. i do not envy someone doing multi layer boards. i had enough trouble with a 2 layer board back in 1988.... never done it since.. lol
Exactly. And it is even more than 5% which must be done by hand because auto-routers generally aren't good for complex and space limited cases. In practice it is almost 100%...
It is like a game where objects can be moved on the screen. And the computer (EDA too) tells (by highlighting) if two objects come too close. If they are too close, it would make problems in production which is a chemical process of etching copper. See this video:

http://boards.openpandora.org/topic/16655-main-pcb-v3-is-finished/

Some of you did wonder why it is so complex to get from v3 to v4, as v3 was done in August and is almost working. Well, the "almost" means that there are missing connections and components. These must be squeezed between the existing ones. Most of the time was spent to design and review the schematics for those missing parts to make it robust. It is the step from a demonstrator prototype to something that potentially can go to mass production - unless further issues reveal themselves. Since you already have seen the demonstrator with 90% of the functions the missing 10% aren't obvious and some are hidden completely but protect you from potential malfunctions.

As you can see in the Video there isn't much room for additional wires. But they have to be routed through the existing maze.

Unfortunately we did run into a problem that no computer can help: there was a mistake in the definition of our EDA tool for the minimum clearance between two wires. So the EDA tool did *not* yell for some conflicts. And everything looked fine, until we got the feedback from the PCB manufacturer that some 100 traces are too close to be produced. Otherwise we would have started to produce the first complete main boards today.

Fortunately it is only more tedious work to fix it by brushing away existing wires and VIAs (plate through) or ripping up parts of the puzzle and closing the new gaps.

Someone asked, how I can be sure that the puzzle can be solved? Well, I am never sure until it is done. I am only confident (and by using the right tool there is an indicator of progress, i.e. how many conflicts have been solved and how many remain - until this value is 0.000000).

Someone else asked why the CPU board is thought to be simpler. There are several factors (which all drive cost up but make CAD work easier):

* we go for 8 instead of 4 layers, i.e. much more 3D space for copper wiring - but this doubles the PCB cost

* we will have smaller traces (100 um or even 75 um instead of 150 um) allowing to meander wires much easier between component connection pads - this increases the PCB cost by some more 20%

* we will have buried and blind VIAs (i.e. not all drills are going from top side to bottom side) so that one signal going from layer 1 to 3 does not block layers 4-8 - this increases the PCB cost again because it needs a different production technology

* we will have Via-In-Pad technology which saves a lot of space connecting a BGA - it would be impossible to connect the OMAP5 without this PCB technology

So by adding a lot of cost per square cm (but on a much smaller total area than the full Pyra main board), there are many more degrees of freedom on the CPU board to get the wiring puzzle solved.

But again, we only know if the puzzle can be solved as soon as it is solved. I.e. as soon as the CPU board layout has 0.00000 conflicts remaining (provided we have defined the clearance rules correctly).

Well, even if we fail, we can start over with 10 layers. Or 12. Or 16. By adding more and more cost, there is a point where it is solvable. But we are not yet at that point of the puzzle to use this escape mode.
Spoiler'd to reduce page size - Binky
 Great post GTA04 thanks for the explanations :)
 
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Inside of that picture are at least 3 major and 8 small rule infringements. If we keep it like that, the PCB could not be produced reliably, would get shortcircuits or similar issues.

Moving traces around could lead to other rule infringements - so this is quite a puzzle (high-level Sokoban, eh?)

Each issue needs about 5 - 30 minutes to solve, so it's possible, just takes a loooot of time.

And the more you solve, the more complicated it gets for the remaining ones... fun.
But how can he be sure that there is an existing solution?
sometimes there is not a solution without a complete redesign of the board layout. some packages can auto route for you but on complicated boards may still only do 95% if you are lucky. the remaining 5% is where the art come in.. loltraces on multi layer boards can be fed through a 3 dimensional maze up and down layers as well as across layers. but those sorts of traces can give other problems with noise and crosstalk of signals. i do not envy someone doing multi layer boards. i had enough trouble with a 2 layer board back in 1988.... never done it since.. lol
Exactly. And it is even more than 5% which must be done by hand because auto-routers generally aren't good for complex and space limited cases. In practice it is almost 100%...
It is like a game where objects can be moved on the screen. And the computer (EDA too) tells (by highlighting) if two objects come too close. If they are too close, it would make problems in production which is a chemical process of etching copper. See this video:

http://boards.openpandora.org/topic/16655-main-pcb-v3-is-finished/

Some of you did wonder why it is so complex to get from v3 to v4, as v3 was done in August and is almost working. Well, the "almost" means that there are missing connections and components. These must be squeezed between the existing ones. Most of the time was spent to design and review the schematics for those missing parts to make it robust. It is the step from a demonstrator prototype to something that potentially can go to mass production - unless further issues reveal themselves. Since you already have seen the demonstrator with 90% of the functions the missing 10% aren't obvious and some are hidden completely but protect you from potential malfunctions.

As you can see in the Video there isn't much room for additional wires. But they have to be routed through the existing maze.

Unfortunately we did run into a problem that no computer can help: there was a mistake in the definition of our EDA tool for the minimum clearance between two wires. So the EDA tool did *not* yell for some conflicts. And everything looked fine, until we got the feedback from the PCB manufacturer that some 100 traces are too close to be produced. Otherwise we would have started to produce the first complete main boards today.

Fortunately it is only more tedious work to fix it by brushing away existing wires and VIAs (plate through) or ripping up parts of the puzzle and closing the new gaps.

Someone asked, how I can be sure that the puzzle can be solved? Well, I am never sure until it is done. I am only confident (and by using the right tool there is an indicator of progress, i.e. how many conflicts have been solved and how many remain - until this value is 0.000000).

Someone else asked why the CPU board is thought to be simpler. There are several factors (which all drive cost up but make CAD work easier):

* we go for 8 instead of 4 layers, i.e. much more 3D space for copper wiring - but this doubles the PCB cost

* we will have smaller traces (100 um or even 75 um instead of 150 um) allowing to meander wires much easier between component connection pads - this increases the PCB cost by some more 20%

* we will have buried and blind VIAs (i.e. not all drills are going from top side to bottom side) so that one signal going from layer 1 to 3 does not block layers 4-8 - this increases the PCB cost again because it needs a different production technology

* we will have Via-In-Pad technology which saves a lot of space connecting a BGA - it would be impossible to connect the OMAP5 without this PCB technology

So by adding a lot of cost per square cm (but on a much smaller total area than the full Pyra main board), there are many more degrees of freedom on the CPU board to get the wiring puzzle solved.

But again, we only know if the puzzle can be solved as soon as it is solved. I.e. as soon as the CPU board layout has 0.00000 conflicts remaining (provided we have defined the clearance rules correctly).

Well, even if we fail, we can start over with 10 layers. Or 12. Or 16. By adding more and more cost, there is a point where it is solvable. But we are not yet at that point of the puzzle to use this escape mode.
Spoiler'd to reduce page size - Binky
Great post GTA04 thanks for the explanations :)
Great quote Bosbeetle thanks for the pyramid :)
 
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Bosbeetle You should edit the post you are replying to, to shorten it.
 
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Oh, this means i ditnt have something to put my new USB 3 Stick on next yeahr??


This makes me cry..


Egal, USB 3 Sticks on USB 2 Port also works...
 
You should still be able to use USB3 devices at USB3 speeds but you would need to connect them to the wide micro-USB connector via a USB3 OTG adapter.

- Neelix
 
I know i can use USB 3 on USB 2 Ports,


Thats no Problem..


Bought the Stick yesterday because i got a 16 and a 32 gb for 22 € in german pandora board ..


The 32 gb to put it in my Car whit Musik, and the 16 as utility Stick for Pyra..
 
you can connect USB3 devices (blue plug) but will get USB2 speed only (480 MBit/s). The big socket has eSATA or USB2. This is similar to USB3 in speed but not compatible.
That's not what I was asking. I know that OMAP5 has only USB2 controllers (except the single USB3 OTG port). The question was whether there is a physical USB3 port soldered in with extra signals routed to the daughterboard connector. This way, we could hope that whenever the daughterboard upgrade comes few years down the line, this USB port could be upgraded to USB3 by replacing the daughterboard. Assuming the chosen SoC has a second USB3 controller, of course.

From your reply I guess that nobody had thought of that. Oh well.
 
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Why ditnt you have a Username, if i may ask??


Ok, i can put my Sticks in Pyra but only whit USB2 Speed..


Some News on the New Prototype Boards and Cases??
 
I can't make USB3 FLASH memory sticks work on my USB2-only PC for whatever reason (they perma mount-unmount-mount-unmount...). So it's good to know that these will work on the Pyra. :)
 
The Pyra is going to have a USB3.0 OTG port.  You can use USB3 devices at USB3 speeds but you need a USB3 OTG adapter to do it.  You can get an adapter/hub combination off Amazon for $14 right now and solve all your problems.
 
I can't make USB3 FLASH memory sticks work on my USB2-only PC for whatever reason (they perma mount-unmount-mount-unmount...). So it's good to know that these will work on the Pyra. :)
The most likely explanation is that they're too power-hungry for your host port. Had a similar problem with an USB3 thumbdrive-sized mini-SSD. It *did* mount, but it quickly hung when something was actually read/written from/to it.

The USB3 standard upped the power supply from 500mA*5V = 2.5W to 900mA*5V = 4.5W. If your stick charges more than 500mA, it might fail to work on a USB2 controller. Some controllers can supply more current than it is required of them by the standard, but it's better not to rely on that. Try a powered hub, it might make the stick work.
 
I guess the little hub I use in my PC Monitor is powered but that also don't helped to make the 3.0 stik work. No clue what was wrong with that stick, it was an normal 32GB USB3.0 memory Stick. Funny thing is that Stick worked perfectly on my Pandora and I doubt that the Pandora offers more USB power than my compared beefy Asus P5Q Mainboard. ;)

However, I have another USB Stick now, only USB 2.0 but works on my Pandora AND on my PC so all is fine. :)
 
you can connect USB3 devices (blue plug) but will get USB2 speed only (480 MBit/s).
Will it be possible to use a USB1 device such as a mouse or keyboard directly plugged into the USB port, i.e. no USB Hub?
 
so pyra in development? when i can buy it and where?
When the development is complete and a when there is a fully working prototype is when EvilDragon said he will allow Pre-orders.. It will be sold at his shop ( http://dragonbox.de) and perhaps other shops.
 
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