Tests, tests, and more tests.

Silent-Hunter

Hardcore Member
Joined
May 29, 2010
Messages
3,094
The 1600 supports DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600.

The DDR3-1866 supports all these but additionally DDR3-1866 (so it's a bit faster, if your SoC supports it).

They always support slower frequencies, just not higher ones.
If the lowest it supports is DDR3-800, doesn't that mean it needs to be 800 MHz?
 

Letalis Sonus

Advanced Member
Joined
Mar 5, 2009
Messages
1,296
If the lowest it supports is DDR3-800, doesn't that mean it needs to be 800 MHz?
There's the effective clock, there's the interface clock and there's the memory clock.

JEDEC specifies DDR3-1600 with an I/O clock of 400MHz and a memory clock of 200 MHz, which results in an effective clock of 1600 MHz. DDR3 performs 4 transactions per clock, resulting in 8x prefetch.

Fun fact: DDR-400 already had a memory clock of 200 MHz, there was no significant increase in memory clock until DDR4.

Edit: Brainfart, I/O clock is 800 MHz. The DDR3 I/O clock is always 4x memory clock.
 
Last edited:

Bosbeetle

Terminally lost
Joined
Sep 7, 2008
Messages
3,730
Age
38
Location
The Netherlands
Website
Visit site
The 1600 supports DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600.

The DDR3-1866 supports all these but additionally DDR3-1866 (so it's a bit faster, if your SoC supports it).

They always support slower frequencies, just not higher ones.
Ah thats clear thanks.. :)
[doublepost=1539028608,1539028430][/doublepost]
I see! That's interesting. So perhaps 400 should be tried then?
Well they also reported running to slow could lead to faults... but I guess 400 and 533 could be tried... still strange OMAP5 spec is 532
 

levi

Still fresh, damnit!
Joined
Oct 6, 2008
Messages
11,604
Location
Somewhere off the coast of the EU
Is it possible it's a typo? And it's really 533 that's the maximum supported?
Assuming that 533 is the IO clock and is in MHz that means an effective RAM speed of 1066MTps or 1.066GTps. I forget if the quickest way to read sequential data to a single register is using an STMID or a separate LDR and SUB ARM mnemonics, and what the clock timings for those are, but it almost certainly takes more than two clock cycles between every access even if you use relative addressing to the start of the ram block and count down to zero using a SUBS then a conditional BNE to provide the loop return path, meaning the maximum usual RAM access rate from the core is clock/3, so about 0.5GTps at 32 bits wide at 1.5GHz clock. If the memory can really be run that fast, it seems as if we don't really need so much caching; I must be missing something, perhaps the DDR RAM is not 32-bits wide or something. If you were doing a simple memcpy analogue and you could afford to push used registers to the stack temporarily and use multiple registers in a STM instruction you could perhaps get the memory bandwidth more saturated.
 

matzesu

Hardcore Member
Staff member
Joined
Oct 24, 2008
Messages
9,286
Age
35
Location
Germany,, Saarland, at home
I understand only Train Station ,
So whit this diverent MHz thing, the 4gb Pyra will work??

Fortunately I have no a lot of EBooks on my Kindle to waste another 2 Months..
 

matzesu

Hardcore Member
Staff member
Joined
Oct 24, 2008
Messages
9,286
Age
35
Location
Germany,, Saarland, at home
No my GPD Win still works like pretty well,
i used it last week to build me a Songbook for my Ebook Reader, but as i have now a XBOX, for my GTA, Farming Sim and Spintires, i ditnt use it much..
The Kindle was pretty atracktive for me because its waterproof and thin,
 
Top