Tests, tests, and more tests.

Discussion in 'Pyra News' started by EvilDragon, Sep 15, 2018.

  1. Silent-Hunter

    Silent-Hunter Advanced Member

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    If the lowest it supports is DDR3-800, doesn't that mean it needs to be 800 MHz?
     
  2. Letalis Sonus

    Letalis Sonus Advanced Member

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    There's the effective clock, there's the interface clock and there's the memory clock.

    JEDEC specifies DDR3-1600 with an I/O clock of 400MHz and a memory clock of 200 MHz, which results in an effective clock of 1600 MHz. DDR3 performs 4 transactions per clock, resulting in 8x prefetch.

    Fun fact: DDR-400 already had a memory clock of 200 MHz, there was no significant increase in memory clock until DDR4.

    Edit: Brainfart, I/O clock is 800 MHz. The DDR3 I/O clock is always 4x memory clock.
     
    Last edited: Oct 9, 2018
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  3. Silent-Hunter

    Silent-Hunter Advanced Member

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    I see! That's interesting. So perhaps 400 should be tried then?
     
  4. Bosbeetle

    Bosbeetle Terminally lost

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    Ah thats clear thanks.. :)
    --- Double Post Merged, Oct 8, 2018, Original Post Date: Oct 8, 2018 ---
    Well they also reported running to slow could lead to faults... but I guess 400 and 533 could be tried... still strange OMAP5 spec is 532
     
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  5. Silent-Hunter

    Silent-Hunter Advanced Member

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    Is it possible it's a typo? And it's really 533 that's the maximum supported?
     
  6. TrashyMG

    TrashyMG Sarcasm Dispenser Staff Member

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    Anything possible, especially with this project in involved.
     
  7. Silent-Hunter

    Silent-Hunter Advanced Member

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    Someone should give 533 a go then!
     
  8. levi

    levi Still fresh, damnit!

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    Assuming that 533 is the IO clock and is in MHz that means an effective RAM speed of 1066MTps or 1.066GTps. I forget if the quickest way to read sequential data to a single register is using an STMID or a separate LDR and SUB ARM mnemonics, and what the clock timings for those are, but it almost certainly takes more than two clock cycles between every access even if you use relative addressing to the start of the ram block and count down to zero using a SUBS then a conditional BNE to provide the loop return path, meaning the maximum usual RAM access rate from the core is clock/3, so about 0.5GTps at 32 bits wide at 1.5GHz clock. If the memory can really be run that fast, it seems as if we don't really need so much caching; I must be missing something, perhaps the DDR RAM is not 32-bits wide or something. If you were doing a simple memcpy analogue and you could afford to push used registers to the stack temporarily and use multiple registers in a STM instruction you could perhaps get the memory bandwidth more saturated.
     
  9. Djoga'Ro

    Djoga'Ro moonstruck

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    @levi According to wikipedia the bus width of DDR3 is 64 bit, but access takes more cycles.
     
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  10. matzesu

    matzesu Advanced Member

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    I understand only Train Station ,
    So whit this diverent MHz thing, the 4gb Pyra will work??

    Fortunately I have no a lot of EBooks on my Kindle to waste another 2 Months..
     
  11. Letalis Sonus

    Letalis Sonus Advanced Member

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    That's the bus width of a whole DIMM, the bus width of the actual DDR chips varies.
     
  12. matzesu

    matzesu Advanced Member

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    Whiteout jokes: I have the Driving License DE which is for a Bus
    So whit this Bus Speed, the Pyra ditnt freez whit the 4gb Board??
     
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  13. dosenfisch

    dosenfisch Still Fresh

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    In the reference manual of the IGEPv5 development board is explicitly stated, that 4GB DDR3 @ 1066MHz are supported by the OMAP5432. Therefore, 533 MHz (1066 MHz effective) should work and the 532 MHz limit is most likely just a typo.
     
  14. Silent-Hunter

    Silent-Hunter Advanced Member

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    That makes sense to me. I can't think of any other explanation.
     
  15. javaJake

    javaJake Jacob Godserv

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    ED, I knew the Pyra was going to be a slow burn so I'm in no hurry. The day I get the preorder fulfilment email will be a nice surprise! :)
     
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  16. sandstein

    sandstein Still Fresh

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    Haha! Is your GPD-Win already broken? Like mine?

    And why didn't you get a Tolino? Tss tss.
     
  17. matzesu

    matzesu Advanced Member

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    No my GPD Win still works like pretty well,
    i used it last week to build me a Songbook for my Ebook Reader, but as i have now a XBOX, for my GTA, Farming Sim and Spintires, i ditnt use it much..
    The Kindle was pretty atracktive for me because its waterproof and thin,
     
  18. Djoga'Ro

    Djoga'Ro moonstruck

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    So, in the Pyra naked RAM chips are used? Aren't they setup to form something electrically equal to a DIMM slot/bus, then?
     
  19. gpsqueeek

    gpsqueeek Member

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    You mean shaved ?
    --> [ -] I'm already faaaar away !
     
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  20. Zwerg01

    Zwerg01 Still Fresh

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    No its not. its 0,19%. And this is the reason why there is so much BS again.
     

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