Silent-Hunter
Hardcore Member
- Joined
- May 29, 2010
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Is it possible it's a typo? And it's really 533 that's the maximum supported?
Anything possible, especially with this project in involved.Is it possible it's a typo? And it's really 533 that's the maximum supported?
Someone should give 533 a go then!Anything possible, especially with this project in involved.
Assuming that 533 is the IO clock and is in MHz that means an effective RAM speed of 1066MTps or 1.066GTps. I forget if the quickest way to read sequential data to a single register is using an STMID or a separate LDR and SUB ARM mnemonics, and what the clock timings for those are, but it almost certainly takes more than two clock cycles between every access even if you use relative addressing to the start of the ram block and count down to zero using a SUBS then a conditional BNE to provide the loop return path, meaning the maximum usual RAM access rate from the core is clock/3, so about 0.5GTps at 32 bits wide at 1.5GHz clock. If the memory can really be run that fast, it seems as if we don't really need so much caching; I must be missing something, perhaps the DDR RAM is not 32-bits wide or something. If you were doing a simple memcpy analogue and you could afford to push used registers to the stack temporarily and use multiple registers in a STM instruction you could perhaps get the memory bandwidth more saturated.Is it possible it's a typo? And it's really 533 that's the maximum supported?
That's the bus width of a whole DIMM, the bus width of the actual DDR chips varies.
Fortunately I have no a lot of EBooks on my Kindle to waste another 2 Months..
So, in the Pyra naked RAM chips are used? Aren't they setup to form something electrically equal to a DIMM slot/bus, then?That's the bus width of a whole DIMM, the bus width of the actual DDR chips varies.
You mean shaved ?naked RAM
We could try overclocking OMAP to 533, it's < 1% overclock so maybe it
pretty sure 0.19% is still less than 1%...No its not. its 0,19%. And this is the reason why there is so much BS again.
Or, if Dodge brings some kind of Beach Buggy Style line onto the market ....You mean shaved ?
--> [ -] I'm already faaaar away !
No its not. its 0,19%. And this is the reason why there is so much BS again.
A DIMM is literally just a plain PCB with a fixed interface, some arbitration circuity and an SPI flash for the SPD - with the SPD being optional on soldered-on RAM, as you can just program fixed timings into the boot loader doing the DDR controller initialization. The DDR chips are really just hooked up in parallel to fill up the available bus width, common bus widths for single DDR3 chips seem to be 4, 8 and 16 bit.So, in the Pyra naked RAM chips are used? Aren't they setup to form something electrically equal to a DIMM slot/bus, then?