Tests, tests, and more tests.

[Silent-Hunter]

I see! That's interesting. So perhaps 400 should be tried then?

 

[Bosbeetle]

The 1600 supports DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600.

The DDR3-1866 supports all these but additionally DDR3-1866 (so it's a bit faster, if your SoC supports it).

They always support slower frequencies, just not higher ones.

Ah thats clear thanks..
[doublepost=1539028608,1539028430][/doublepost]

I see! That's interesting. So perhaps 400 should be tried then?

Well they also reported running to slow could lead to faults... but I guess 400 and 533 could be tried... still strange OMAP5 spec is 532

 

[Silent-Hunter]

Is it possible it's a typo? And it's really 533 that's the maximum supported?

 

[TrashyMG]

Is it possible it's a typo? And it's really 533 that's the maximum supported?

Anything possible, especially with this project in involved.

 

[Silent-Hunter]

Anything possible, especially with this project in involved.

Someone should give 533 a go then!

 

[levi]

Is it possible it's a typo? And it's really 533 that's the maximum supported?

Assuming that 533 is the IO clock and is in MHz that means an effective RAM speed of 1066MTps or 1.066GTps. I forget if the quickest way to read sequential data to a single register is using an STMID or a separate LDR and SUB ARM mnemonics, and what the clock timings for those are, but it almost certainly takes more than two clock cycles between every access even if you use relative addressing to the start of the ram block and count down to zero using a SUBS then a conditional BNE to provide the loop return path, meaning the maximum usual RAM access rate from the core is clock/3, so about 0.5GTps at 32 bits wide at 1.5GHz clock. If the memory can really be run that fast, it seems as if we don't really need so much caching; I must be missing something, perhaps the DDR RAM is not 32-bits wide or something. If you were doing a simple memcpy analogue and you could afford to push used registers to the stack temporarily and use multiple registers in a STM instruction you could perhaps get the memory bandwidth more saturated.

 

[Djoga'Ro]

@levi According to wikipedia the bus width of DDR3 is 64 bit, but access takes more cycles.

 

[matzesu]

I understand only Train Station ,
So whit this diverent MHz thing, the 4gb Pyra will work??

Fortunately I have no a lot of EBooks on my Kindle to waste another 2 Months..

 

[Letalis Sonus]

@levi According to wikipedia the bus width of DDR3 is 64 bit, but access takes more cycles.

That's the bus width of a whole DIMM, the bus width of the actual DDR chips varies.

 

[matzesu]

Whiteout jokes: I have the Driving License DE which is for a Bus
So whit this Bus Speed, the Pyra ditnt freez whit the 4gb Board??

 

[dosenfisch]

In the reference manual of the IGEPv5 development board is explicitly stated, that 4GB DDR3 @ 1066MHz are supported by the OMAP5432. Therefore, 533 MHz (1066 MHz effective) should work and the 532 MHz limit is most likely just a typo.

 

[Silent-Hunter]

That makes sense to me. I can't think of any other explanation.

 

[javaJake]

ED, I knew the Pyra was going to be a slow burn so I'm in no hurry. The day I get the preorder fulfilment email will be a nice surprise!

 

[sandstein]

Fortunately I have no a lot of EBooks on my Kindle to waste another 2 Months..

Haha! Is your GPD-Win already broken? Like mine?

And why didn't you get a Tolino? Tss tss.

 

[matzesu]

No my GPD Win still works like pretty well,
i used it last week to build me a Songbook for my Ebook Reader, but as i have now a XBOX, for my GTA, Farming Sim and Spintires, i ditnt use it much..
The Kindle was pretty atracktive for me because its waterproof and thin,

 

[Djoga'Ro]

That's the bus width of a whole DIMM, the bus width of the actual DDR chips varies.

So, in the Pyra naked RAM chips are used? Aren't they setup to form something electrically equal to a DIMM slot/bus, then?

 

[gpsqueeek]

naked RAM

You mean shaved ?
--> [ -] I'm already faaaar away !

 

[Zwerg01]

We could try overclocking OMAP to 533, it's < 1% overclock so maybe it

No its not. its 0,19%. And this is the reason why there is so much BS again.

 

[TrashyMG]

No its not. its 0,19%. And this is the reason why there is so much BS again.

pretty sure 0.19% is still less than 1%...

 

[Djoga'Ro]

You mean shaved ?
--> [ -] I'm already faaaar away !

Or, if Dodge brings some kind of Beach Buggy Style line onto the market ....