- Jan 18, 2010
DLL in this sense means Delay Locked Loop, not the crap Windows libraries. It's memory timings and what not.
Back in the day when I messed around with PIC16f, pretty much all of the power related stuff was implemented with magic registers. For instance, changing the clock rate was writing a divider value to an oscillator configuration register and 1 (or 2, I can't remember what the manual said off the top of my head) clock cycles later the processor was using the new frequency. If you needed precise timing then you would calculate the time it took to reconfigure the oscillator by using the old frequency. When I went through a PIC class one of our first tasks was to make a cycle-accurate delay function, which involved looking up and verifying the precise execution time of every instruction we used (including setup and execution of function calls).How do power state changes work, anyway? Does the software issue a special instruction or write some specific value to a particular register and the SoC does the rest? Or does the software have to handle some management around it, too?
Well, seeing how Tony wrote in the mailing list:
, it seems this is not the first time someone has done that (or at least he did that).Well for the idle freezing issue, curiously the old "disable internal dll" trick seems to work.
This makes it sound to me that the solution is not simply to enable that for production use, but rather that this just seems to be a way to test whether the DLL timings are correctly configured.If that works for the idle system problem, then we probably have some DLL timing related value misconfigured.
It was actually us, after the first 4GB boards were made and had problems, setting that bit had positive effects. I don't remember who came up with setting that bit back then, zmatt maybe.
Just noticed: Clock rate and data rate are different.
For example, for the IMGTech memory, the website says:
Data Rate: DDR3-1333
Clock Rate: 667MHz
And the Samsung Data sheet says:
400 MHz f CK for 800Mb/sec/pin, 533MHz f CK for 1066Mb/sec/pin,
667MHz f CK for 1333Mb/sec/pin, 800MHz f CK for 1600Mb/sec/pin,
933MHz f CK for 1866Mb/sec/pin,
So 533MHz should be fine.
The 1600 supports DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600.So we "have" 1600 DDR3L --> how should than 533 be okay?