Tests, tests, and more tests.

Discussion in 'Pyra News' started by EvilDragon, Sep 15, 2018.

  1. TrashyMG

    TrashyMG Sarcasm Dispenser Staff Member

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    DLL in this sense means Delay Locked Loop, not the crap Windows libraries. It's memory timings and what not.
     
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  2. Silent-Hunter

    Silent-Hunter Advanced Member

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  3. Djhg2000

    Djhg2000 Very Active Member

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    Back in the day when I messed around with PIC16f, pretty much all of the power related stuff was implemented with magic registers. For instance, changing the clock rate was writing a divider value to an oscillator configuration register and 1 (or 2, I can't remember what the manual said off the top of my head) clock cycles later the processor was using the new frequency. If you needed precise timing then you would calculate the time it took to reconfigure the oscillator by using the old frequency. When I went through a PIC class one of our first tasks was to make a cycle-accurate delay function, which involved looking up and verifying the precise execution time of every instruction we used (including setup and execution of function calls).

    Now an ARM is far more complex than a PIC, but they both have roots in old RISC designs so it's not impossible the same workflow simply got inherited from the existing designs.
     
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  4. levi

    levi Still fresh, damnit!

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    The ARM design was heavily influenced by the 6502, so thing like video controller registers always used to be memory mapped on those old 8-bit machines. I suspect that's the simplest way to add things to an ARM core via customising the MMU rather than adding registers into an already compact and tightly laid out core.
     
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  5. Grench

    Grench Forum Addict!

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    https://xkcd.com/303/

    Sorry - had to be done.
     
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  6. WizardStan

    WizardStan Mega GP Mania

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    Ah yes, of course. To prevent a lock you must add a loop to delay it. :p
     
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  7. Silent-Hunter

    Silent-Hunter Advanced Member

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    I hope this is really it, and the issue is fixed!
     
  8. notaz

    notaz Certified Guru

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    With that patch my pyra has clocked over 3h (and counting), something I could ever reach only with memtest before. I'll see if it survives overnight.

    I remember @zmatt saying DDR_DISABLE_DLL is not supposed to be ever set. I wonder what the repercussions are because nobody else seem to set it.
     
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  9. EvilDragon

    EvilDragon Administrator Staff Member

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    Well, seeing how Tony wrote in the mailing list:
    , it seems this is not the first time someone has done that (or at least he did that).

    And further from his post:
    This makes it sound to me that the solution is not simply to enable that for production use, but rather that this just seems to be a way to test whether the DLL timings are correctly configured.

    So if I understood him correctly, is simply tells us WHAT the problem is (wrong DLL timings), it's not the fix.
     
  10. notaz

    notaz Certified Guru

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    It was actually us, after the first 4GB boards were made and had problems, setting that bit had positive effects. I don't remember who came up with setting that bit back then, zmatt maybe.
     
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  11. Silent-Hunter

    Silent-Hunter Advanced Member

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    Well at least now you know what it (hopefully) is.
     
  12. Linux-SWAT

    Linux-SWAT Hardcore Member

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    Starting tomorrow, I'll stay next to my post box the whole day.
     
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  13. rSl

    rSl **** COMMODORE 64 PYRA V2 **** 4GB RAM SYSTEM

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    ++++1
     
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  14. fusion_power

    fusion_power Advanced Member

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    That compared little software pieces/commands can cause such massive hardware issues...scary...:confused:
     
  15. FBnil

    FBnil Waterfox > firefox

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    wewaited2months-small.jpg
     
  16. comradekingu

    comradekingu Glowing ember

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    How does SPD settings work on ARM?

    etutorials.org/Linux+systems/embedded+linux+systems/Chapter+9.+Setting+Up+the+Bootloader/9.5+U-Boot/
    was interesting.

    Is "clocks_in_mhz" 1 or 0 in uboot?

    Since it seems a bit random, maybe it is a scaling issue? Changing the multiplier, FSB/bclk or voltage could be problematic.

    Then again I dont know how an OMAP5 overclocks.
     
  17. Bosbeetle

    Bosbeetle Terminally lost

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    Looks like the tangled ball of yarn is unravalling a bit, whoop!
     
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  18. Linux-SWAT

    Linux-SWAT Hardcore Member

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  19. Bosbeetle

    Bosbeetle Terminally lost

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    So we "have" 1600 DDR3L --> how should than 533 be okay? Since it not a multiple of 533. If it is 1600 Mb over 4 pins it should be at 400MHz... if it's 1600 over 2 pins it should be 800MHz. Should setting it to 400 MHz be an option.

    If 532 is the max for OMAP5 400MHz would be a safe bet :p
     
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  20. EvilDragon

    EvilDragon Administrator Staff Member

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    The 1600 supports DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600.

    The DDR3-1866 supports all these but additionally DDR3-1866 (so it's a bit faster, if your SoC supports it).

    They always support slower frequencies, just not higher ones.
     
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