Tests, tests, and more tests.

Letalis Sonus

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Mar 5, 2009
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So, in the Pyra naked RAM chips are used? Aren't they setup to form something electrically equal to a DIMM slot/bus, then?
A DIMM is literally just a plain PCB with a fixed interface, some arbitration circuity and an SPI flash for the SPD - with the SPD being optional on soldered-on RAM, as you can just program fixed timings into the boot loader doing the DDR controller initialization. The DDR chips are really just hooked up in parallel to fill up the available bus width, common bus widths for single DDR3 chips seem to be 4, 8 and 16 bit.
 

Djoga'Ro

moonstruck
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A DIMM is literally just a plain PCB with a fixed interface, some arbitration circuity and an SPI flash for the SPD - with the SPD being optional on soldered-on RAM, as you can just program fixed timings into the boot loader doing the DDR controller initialization. The DDR chips are really just hooked up in parallel to fill up the available bus width, common bus widths for single DDR3 chips seem to be 4, 8 and 16 bit.
Does anybody know what the bus width is between the SoC and the RAM setup in the Pyra? I'm curious.
 

levi

Still fresh, damnit!
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Does anybody know what the bus width is between the SoC and the RAM setup in the Pyra? I'm curious.
According to the schematic published last year, the chips are each MT41K256M16HAs. I can find MT41K256M32's on the internet and those seem to be 32-bit parts, but given ours have M16 in their name and the fact they only seem to have 16 numbered lines beginning with D, I think they're 16 bit parts. There are four of them, two per channel. I'm not familiar with the way these things are actually logically laid out, so perhaps that's two 32-bit buses rather than one 64-bit one, which would perhaps make sense as the ARM chip's MMU is defined in 32-bit chunks.
 

Silent-Hunter

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May 29, 2010
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Isn't on-die termination(ODT) important? If it doesn't work, will the Pyra still be stable, or will there be signal reflection?
 

levi

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Terminators need to match the line's characteristic impedance. The short lines from one chip to adjacent ram chips on a small PCB are super short and very pure so I'd expect they have very low impedences, but that's just an educated guess to be fair.
 

Confuzzled

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Oct 1, 2018
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For those of you reading that email and wondering what DYN_ODT is, it is Dynamic On-Die Termination, which is explained quite well in this Micron Datasheet in Portable Document Format (pdf):
TN-41-04 DDR3 Dynamic On-Die Termination - Micron - Technical Note - DDR3 Dynamic On-Die Termination
Dynamic ODT enables the DRAM to switch between HIGH or LOW termination impedance without issuing a mode register set (MRS) command. This is advantageous because it improves bus scheduling and decreases bus idle time.
(Apologies: an admin or moderator will need to remove the carets from the above as the board software thinks it may be spam.) Done - Binky
 
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CommanderB

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Mar 1, 2014
Messages
117
Mhm so it is possible that another hardware revision for the CPU board is necessary?

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