Are you sure it's not the TWL6030 or some other product? The TWL6040 appears to be for audio.
Ah, sorry, yes! It's the TWL6037
That's what happens when you post it without checking the schematics...
But back to the 4GB RAM--isn't the issue that your 1.35V rail dropped out of spec by the time it reached your RAM, but was still regulated to 1.35V at the source? Even if you try to minimize IR drops, fundamentally isn't there still a discrepancy between where this rail is regulated and what voltage is at the RAM? You mentioned the PALMAS chip is responsible for regulation--does it monitor the 1.35V at the source or does it monitor the voltage at the RAM?
As far as I know, the OMAP5 is constantly being regulated by the PALMAS (via a communication line, if I'm not mistaken).
The DDR is directly connected to the OMAP5 (even the power), and I'm not sure whether that's even regulated or whether it is just set to one fixed value.
I THINK it's the latter one, as we can set the voltage via software.
The RAM just needs something between a minimum and maximum voltage and will work.
I'm curious about the margining--it seems the lower spec limit for the RAM is 1.215V based on the graphic, and we're getting down to 1.245V in simulation with the improved layout? So, that's 2.4% (30mV) of margin--is that enough margin for component/manufacturing variability and any possible discrepancies between simulation & real-world? Does the 2.4% budget in transient response (is this a DC simulation? I'm curious as to how low those 1.245V nodes go in a transient response)? Are any of these traces accessible (perhaps with minor hacking if need be?) with a multimeter for correlation to simulation (I know the memory is a FBGA package, so probing the individual nodes is unrealistic, but I was wondering if there were some other point on the 1.35V rail that could be probed for correlation)?
The simulation is pretty accurate, no worries about that.
The IBIS files and all other information from the chip manufacturers usually include such tolerances. It wouldn't help much if you simulated everything knowing it still might not work
Juliano and Nikolaus might be able to tell you more about all that, I'm no expert here, I'm trying to understand everything as well.
Lastly (sorry for all the questions!), what determined the 1.35V +/- 10% spec in the graphic? My impression is that the Pyra uses DDR3L, which I thought has a lower spec of 1.283V?
As far as I know, the tolerance limits are ON TOP of the voltages, so 1.283V +/- tolerance is the lowest voltage the RAM HAS to work.
Don't forget: We already have some CPU boards that work with 4GB RAM even though the simulated voltage drop on our current CPU board goes down to about 1.13V (AFAIR correctly)
Important to remember: The given tolerances and voltages for DDR means: They HAVE to work with that setup!
So the manufacturer has to make sure these settings work - and as they also have tolerances in production, they have to widen that margin as well, so RAM will work with less power than needed.
And: We can ADJUST the voltage. So we could easily increase the voltage to 1.36V or 1.37V if need be. But the old PCB still had a too high drop for that.
