This has been discussed a lot in various threads by several people, and I talked to notaz who said he'd talk to ED, but as far as I know ED hasn't commented on it. So I thought I'd ask in a thread here. The concern is that if Pyra is moving to either 2x1GB or 4x1GB chips it'll mean that the 2GB solution only has a 32-bit bus, halving bandwidth vs the original 4x512MB setup or the new 4x1GB one. This could hurt performance for some applications and most likely the GPU performance would be hit the hardest of anything. It's possible that the new 1GB chips use a 32-bit bus, but I doubt it because it'd mean a new CPU board is necessary to accommodate this. And the 4x1GB version would have to use multiple chip-select lines (assuming it's even available on OMAP5). Could we get a confirmation on this matter? Thanks.