it's a bit like looking for the needle in the hay stack.
So what are the Cases doing ?
After reading up on it the other day, I wonder how well the simulation simulated all of the capacitance effects caused by current passing between a power or signal line and ground with an insulator (the board) in between.
Actually I wonder if the caches need considering. Perhaps the active code in the kernel and the memtester can all fit inside a cache, so when you're testing that configuration, you're not actually hitting the ram at all. Once you have a kernel with all kinds of modules inserted, some of those will probably need to live off cache, and it'll need to refill the cache from ram. If that's going awry, perhaps because of RAM timings, or something esoteric in the MMU config, it could be hard for the kernel to report before hitting a duff instruction, and especially if the exception table is out of cache at present, it could have trouble bringing that back in from RAM. I don't know off hand if zero page (where the exception vector tables are normally stored) is protected in some way.
7. 4GB RAM boards were working with only 2GB RAM enabled (as far as I remember - as that was the reason I ordered the RAM modules back then!)
Well, when the unit is sitting around idling, it also doesn't do much to the memory.
And it freezes randomly - up until it freezes, you can do anything, even run memory-intense programs or compile.
Well, if that's true, It's pretty clear for me what to do.
Enable only 2 GB and ship them. As long as these are stable it's fine.
Then you have money and can sleep well until someone figures out what's the issue.
I wonder why no one else mentioned that. It's obvious.