.sdram_config_init = \
(3 << 29) /* SDRAM_TYPE: 3 = DDR3, 4 = LPDDR2 */ \
| (0 << 27) /* IBANK:Internal Bank Position */ \
| (1 << 24) /* DDR_TERM: DDR3 Termination resistor value */ \
| (1 << 23) /* DDR2_DDQS: DDR2 Differential DDQS. 1 for compat */ \
| (0 << 21) /* DYN_ODT: DDR3 Dynamic ODT. Not supported */ \
| (0 << 20) /* DDR_DISABLE_DLL: Disable DLL */ \
| (1 << 18) /* SDRAM_DIVE: DDR3, 0 for RZq/6 and 1 for RZQ/7 (DDR_TERM?) */ \
| (1 << 16) /* CWL: DDR3 CAS Write Latency 0=5, 1=6, 2=7, 3=8 */ \
| (0 << 14) /* NARROW_MODE: 0=32 bit, 1=16 bit. Only 32 bit supported */ \
| (6 << 10) /* CL: CAS Latency (RL) DDR2, 3=3clocks, 4=4, 5=5, 6=6, 7=7, 8=8 */ \
/* DDR3 2=5clocks, 4=6, 6=7, 8=8, 10=9, 12=10, 14=11 */
| (7 << 7) /* ROWSIZE: 0=9 through 7=16 row bits */ \
| (3 << 4) /* IBANK: Internal banks of SDRam: 0=1, 1=2, 2=4,3=8 */ \
| (1 << 3) /* EBANK: External Chip Select Setup 0=NCS0 only. 1=NCS[1:0] */ \
| (2 << 0) /* PAGESIZE: 0=256word (8cols), 1=512word (9cols), 2=1024, 3=2048 */,
.sdram_config = \
(3 << 29) /* SDRAM_TYPE: 3 = DDR3, 4 = LPDDR2 */ \
| (0 << 27) /* IBANK:Internal Bank Position */ \
| (1 << 24) /* DDR_TERM: DDR3 Termination resistor value */ \
| (1 << 23) /* DDR2_DDQS: DDR2 Differential DDQS. 1 for compat */ \
| (0 << 21) /* DYN_ODT: DDR3 Dynamic ODT. Not supported */ \
| (0 << 20) /* DDR_DISABLE_DLL: Disable DLL */ \
| (1 << 18) /* SDRAM_DIVE: DDR3, 0 for RZq/6 and 1 for RZQ/7 (DDR_TERM?) */ \
| (1 << 16) /* CWL: DDR3 CAS Write Latency 0=5, 1=6, 2=7, 3=8 */ \
| (0 << 14) /* NARROW_MODE: 0=32 bit, 1=16 bit. Only 32 bit supported */ \
| (6 << 10) /* CL: CAS Latency (RL) DDR2, 3=3clocks, 4=4, 5=5, 6=6, 7=7, 8=8 */ \
/* DDR3 2=5clocks, 4=6, 6=7, 8=8, 10=9, 12=10, 14=11 */
| (7 << 7) /* ROWSIZE: 0=9 through 7=16 row bits */ \
| (3 << 4) /* IBANK: Internal banks of SDRam: 0=1, 1=2, 2=4,3=8 */ \
| (1 << 3) /* EBANK: External Chip Select Setup 0=NCS0 only. 1=NCS[1:0] */ \
| (2 << 0) /* PAGESIZE: 0=256word (8cols), 1=512word (9cols), 2=1024, 3=2048 */,
.sdram_config2 = 0x0,
.ref_ctrl = \
(1 << 31) /* INITREF_DIS: Initialization and Refresh disable. 1=disable */ \
| (0 << 29) /* SRT: DDR3 Self Refresh temp range. 0=normal*/ \
| (0 << 28) /* ASR: DDR3 Auto Self Refresh. 1=enable*/ \
| (0 << 24) /* PASR: Partial Array Self Refresh */ \
| (0x40F1 << 0) /* REFRESH_RATE: Refresh Rate (< 6*T_RFC) */,
.ref_ctrl_final = \
(0 << 31) /* INITREF_DIS: Initialization and Refresh disable. 1=disable */ \
| (0 << 29) /* SRT: DDR3 Self Refresh temp range. 0=normal*/ \
| (0 << 28) /* ASR: DDR3 Auto Self Refresh. 1=enable*/ \
| (0 << 24) /* PASR: Partial Array Self Refresh */ \
| (0x1035 << 0) /* REFRESH_RATE: Refresh Rate (< 6*T_RFC) */,
.sdram_tim1 = \
((8-1) << 29) /* 7 T_RTW: between Read to Write data phases.*/ \
| ((8-1) << 25) /* 7 T_RP: Precharge to Activate or Refresh. */ \
| ((8-1) << 21) /* T_RCD: Activate to Read or Write. */ \
| ((8-1) << 17) /* T_WR: last Write transfer to Precharge. */ \
| ((20-1) << 12) /* T_RAS: Activate to Precharge. >= T_RCD value */ \
| ((28-1) << 6) /* 27 T_RC: Activate to Activate. */ \
| ((4-1) << 3) /* 7 T_RRD: Activate to Activate for a different bank. For an 8-bank, ((tFAW / (4 × tCK)) - 1) */ \
| ((4-1) << 0) /* T_WTR: last Write to Read. */,
.sdram_tim2 = \
((4-1) << 28) /* T_XP: from power-down exit to any command other than a read command */ \
| (0 << 25) /* T_ODT: from ODT enable to write data driven for DDR3. Must be equal to tAONPD */ \
| ((281+6-1) << 16) /* T_XSNR: 'T_RFC+6' Self-Refresh exit to any command other than a Read command. For DDR3, the value of tXS must be programmed. */ \
| ((512-1) << 6) /* T_XSRD: from Self-Refresh exit to a Read command. For DDR3, the value of tXSDLL must be programmed. */ \
| ((4-1) << 3) /* T_RTP: for the last read command to a Precharge command */ \
| ((4-1) << 0) /* T_CKE: between CKE pin changes */,
.sdram_tim3 = \
(4 << 28) /* T_PDLL_UL: cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks */ \
| ((3-1) << 24) /* T_CSTA: between write-to-write or read-to-read data phases to different chip selects. */ \
| ((4+1-1) << 21) /* T_CKESR: 'T_CKE+1' cycles for which SDRAM must remain in Self Refresh */ \
| ((64-1) << 15) /* ZQ_ZQCS: cycles for a ZQCS command. */ \
| ((1-1) << 13) /* T_TDQSCKMAX: clock that satisfies tDQSCKmax for LPDDR2. */ \
| ((281-1) << 4) /* T_RFC: DDR clock cycles from Refresh or Load Mode to Refresh or Activate.*/ \
| (8 << 0) /* T_RAS_MAX: Maximum number of REFRESH_RATE intervals from Activate to Precharge command */,
.read_idle_ctrl = /* EMIF_DLL_CALIB_CTRL*/ \
(14 << 16) /* ACK_WAIT: Ack Wait, time after phy_dll_calib */ \
| (8 << 0 ) /* DLL_CALIB_INTERVAL: Interval between phy_dll_calib generation*/,
.zq_config = \
(1 << 31) /* ZQ Calibration on CS1 */ \
| (1 << 30) /* ZQ Calibration on CS0*/ \
| (0 << 29) /* ZQ Dual Calib. Needs resistor */ \
| (1 << 28) /* ZQ Self Refresh on exit */ \
| (0 << 27) /* ZQ Self Refresh on Power Down*/ \
| ((2-1) << 18) /* Number of ZQCL make ZQINIT (minus 1)*/ \
| ((4-1) << 16) /* Number of ZQCS intervals that make up ZQCL (minus 1) */ \
| (0x190B << 0) /* Refresh periods between ZQCS */,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = \
(0 << 27) /* RDLVL_MASK: mask read data eye training. Incremental training should be disabled */ \
| (0 << 26) /* RDLVLGATE_MASK: mask dqs gate training. Incremental training should be disabled */ \
| (0 << 25) /* WRLVL_MASK: mask write leveling training. Incremental training should be disabled */ \
| (1 << 21) /* PHY_HALF_DELAYS: 2x mode (MDLL clock is half Phy), 0: 1x mode (MDLL is same as PHY) */ \
| (1 << 20) /* PHY_CLK_STALL_LEVELEnable variable idle for normal operation.*/ \
| (0 << 19) /* PHY_DIS_CALIB_RST: Disable dll_calib. Debug only */ \
| (1 << 18) /* PHY_INVERT_CLK_OUT: Invert DRAM clock. 0 for LDDDR2 */ \
| (16 << 10) /* PHY_DLL_LOCK_DIFF: Max # delay line taps variation while maintaining the master DLL lock */ \
| (0 << 9) /* PHY_FAST_DLL_LOCK: Master DLL to lock fast or average logic must be part of locking process*/ \
| (10 << 0) /* READ_LATENCY: RL + reg_phy_rdc_we_to_re -1.*/,
.emif_ddr_phy_ctlr_1 = \
(0 << 27) /* 1: mask read data eye training. Incremental training should be disabled */ \
| (0 << 26) /* 1: mask dqs gate training. Incremental training should be disabled */ \
| (0 << 25) /* 1: mask write leveling training. Incremental training should be disabled */ \
| (1 << 21) /* 1: 2x mode (MDLL clock is half Phy), 0: 1x mode (MDLL is same as PHY) */ \
| (1 << 20) /* Enable variable idle for normal operation.*/ \
| (0 << 19) /* Disable dll_calib. Debug only */ \
| (1 << 18) /* Invert DRAM clock. 0 for LDDDR2 */ \
| (16 << 10) /* Max # delay line taps variation while maintaining the master DLL lock */ \
| (0 << 9) /* Master DLL to lock fast or average logic must be part of locking process*/ \
| (10 << 0) /* READ_LATENCY = RL + reg_phy_rdc_we_to_re -1.*/,
.emif_ddr_ext_phy_ctrl_1 = \
(0x040 << 20) /* DLL Ratio Phy 2 */ \
| (0x100 << 10) /* DLL Ratio Phy 1 */ \
| (0x100 << 0 ) /* DLL Ratio Phy 0 */,
.emif_ddr_ext_phy_ctrl_2 = \
(0x0B7 << 22) /* DQS Phy 1 Rank 0 */ \
| (0x0B7 << 11) /* DQS Phy 0 Rank 1 */ \
| (0x0B7 << 0 ) /* DQS Phy 0 Rank 0 */,
.emif_ddr_ext_phy_ctrl_3 = \
(0x0B7 << 23) /* DQS Phy 2 Rank 1 */ \
| (0x0B7 << 12) /* DQS Phy 2 Rank 0 */ \
| (0x0B7 << 1 ) /* DQS Phy 1 Rank 1 */,
.emif_ddr_ext_phy_ctrl_4 = \
(0x0B7 << 13) /* DQS Phy 3 Rank 1 */ \
| (0x0B7 << 2 ) /* DQS Phy 3 Rank 0 */,
.emif_ddr_ext_phy_ctrl_5 = 0x4350D435 /*Should be auto filled?*/,
.emif_rd_wr_lvl_rmp_win = 0x00000000 /* Not supported */,
.emif_rd_wr_lvl_rmp_ctl = (1 << 31) /* Full leveling trigger */,
.emif_rd_wr_lvl_ctl = (1 << 31) /* Full leveling trigger */ ,
.emif_rd_wr_exec_thresh = /* EMIF_READ_WRITE_EXECUTION_THRESHOLD */ \
(0 << 31) /* MFLAG_OVERRIDE: MFlag Override*/ \
| (1 << 30) /* LL_BUBBLE_ENABLE. Allows burst access*/ \
| ((4-1) << 8) /* WR_THRSH: Number of write bursts (minus 1)*/ \
| ((6-1) << 0) /* RD_THRSH: Number of read bursts (minus 1)*/
