HackModford
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So basically the only way to keep better compatibility/speed is to mess with gles2n64?
Yeah, there isn't much left to do on the dynarec. If I get bug reports, I'll investigate, but I've fixed all the problems that I know of.HackModford said:So basically the only way to keep better compatibility/speed is to mess with gles2n64?
Ari64 said:At some point I will probably look into merging the dynarec with 1.99.3. I haven't done anything on that yet, so if someone else wants to try it then go ahead.
There are a few improvements in the new version, but the overall compatibility rate hasn't changed much. The reason for moving to the new version would be to use future plugins that are designed for v2.0. There isn't any immediate benefit, it's more of a long-term goal.milkshake said:Would this have any benefits for the pandora version? as in are there any improvements to come from merging with 1.99.3?
The faster memory access and larger cache of the OMAP4 might improve performance. Currently there is limited multi-thread support so there would be little to gain from dual cores. It would be possible to do graphics or audio on the second CPU, but the current code is not written that way.IzzehO said:Just a slightly OT question:
With the release of the Panda Board and it's awesome specs: How well is this emulator going to scale across a dual core and would you consider performance increase to be significant on the newer OMAP4430's? I'm definitely looking forward to what the next generation will do for console emulation and am seriously considering picking up a Panda Board just to be the first to try getting GoldenEye at 30fps
Ari64 said:The faster memory access and larger cache of the OMAP4 might improve performance. Currently there is limited multi-thread support so there would be little to gain from dual cores. It would be possible to do graphics or audio on the second CPU, but the current code is not written that way.
I don't think the SGX540 drivers have been published yet, so you won't be playing Goldeneye on your PandaBoard.
The recompiler is pretty efficient. It might be possible to do some sort of HLE, but I don't have any really good ideas.Schnatterplatsch said:Since I haven't watched the developement, can somebody tell me how much space for (I guess you could kill this word) "optimations" there still is? What are the next steps?
A lot of the time is spent waiting for the L2 cache. Higher clock speed is helpful if it speeds up the cache. OoOE might help if the processor can do something else while waiting for a memory access.Exophase said:You don't think the higher clock speeds, OoOE, and shorter pipeline length will help too?
It would solve a lot of the issues that have come up with the SGX530 drivers.Exophase said:It'd be cool if a really, really optimized software renderer could run on one of the 1GHz Cortex-A9 + NEON cores. I don't really know if this is feasible or not, but I have a good feeling that it'd have to use some radically different techniques than anything yet done for software rendering N64.
All of the hidden costs that could pile up when you start interfacing OGL ES 2 make me nervous.
Ari64 said:A lot of the time is spent waiting for the L2 cache. Higher clock speed is helpful if it speeds up the cache. OoOE might help if the processor can do something else while waiting for a memory access.
Ari64 said:It would solve a lot of the issues that have come up with the SGX530 drivers.
Given the relatively small textures and low polygon count on the N64, a software renderer would primarily be fill rate limited. I don't have a really good idea of how many million pixels/sec this would require at various resolutions.
I'm not sure exactly what the bottleneck is, but the OMAP3530 is using many more cycles than the number of instructions executed.Exophase said:The point I'm making is precisely that on Cortex-A8, a blocking in-order architecture, a bulk of the time spent stalling for memory is not spent doing something else, so that's always time spent in additional to the time spent NOT doing that. In other words, improving the instructions per cycle during and decreasing the cycle time during the times when you are not stalling will still improve throughput even if you stall for the same amounts. Memory access is not a "bottleneck", even if it's the largest contributing factor to performance degradation (technically I don't think you've proven this). OoOE will also reduce the stall amounts like you say.
The branch misprediction penalty can be reduced by resolving the branch early. I don't know if A9 is capable of that, but other chips do this (eg PowerPC).Exophase said:The load-use time hasn't changed from Cortex-A8 so of course the L1 cache is faster (or effectively so anyway). The branch misprediction penalty being lower a lot since that's not something that can be hid with OoOE.
The bilinear filtering on the actual N64 hardware isn't perfect, and there are some noticable artifacts when viewing textures at oblique angles. I doubt it really does all those loads per pixel. It probably just does one load and interpolates against the previous values if the increment is less than one texel. It looks weird at angles where you've got interpolation along one axis and aliasing along the other.Exophase said:I wasn't really thinking about software rendering at higher than N64 resolutions. The bilinear filtering is what's going to really cost you, since you don't have any kind of scatter gather in the SIMD and have to do all those loads per-pixel. The DSP might be better at it.
Ari64 said:I'm not sure exactly what the bottleneck is, but the OMAP3530 is using many more cycles than the number of instructions executed.
Ari64 said:The branch misprediction penalty can be reduced by resolving the branch early. I don't know if A9 is capable of that, but other chips do this (eg PowerPC).
Ari64 said:The bilinear filtering on the actual N64 hardware isn't perfect, and there are some noticable artifacts when viewing textures at oblique angles. I doubt it really does all those loads per pixel. It probably just does one load and interpolates against the previous values if the increment is less than one texel. It looks weird at angles where you've got interpolation along one axis and aliasing along the other.
notaz said:It seems we have "speculative accesses on AXI" enabled in Cortex, and according to this:
http://lists.denx.de...ary/067534.html
it should be better disabled. What do you guys think?
notaz said:BTW, if you look at 3.2.43 in the manual, there are some cool performance counters supported by A8, and it's possible to have user mode access to then. I can give a module that enables user mode access if anyone wants to play with this.
What Intel does is to fuse a compare+branch into a single macro-op. This then goes into the reorder buffer and can be issued early if there are no dependencies.Exophase said:That's not OoOE per-se. PowerPC is the only popular architecture I'm aware of that can do this implicitly. The ISA design (multiple CRs and a much closer match between flags and conditions) there lends itself much better to this than a traditional flags design. ARM at least has the benefit of letting you not set flags on ALU operations, but you still don't know which condition code you're going to have to predict for. I guess you'd predict all 14 and have the BTB encode the condition code and use the two to predict.
I don't know what it's actually doing, I just remember seeing the odd glitches. It's very noticable in OoT where you can walk right up to the walls.Exophase said:What I've read is that N64 uses a triangular pattern, ie 3 loads per pixel instead of 4. What you're describing would still be almost as bad in software rendering, don't you think?
I don't know what it does, but I assumed it was doing data prefetches (which could potentially block code fetches).Exophase said:notaz said:It seems we have "speculative accesses on AXI" enabled in Cortex, and according to this:
http://lists.denx.de...ary/067534.html
it should be better disabled. What do you guys think?
Definitely worth a shot. The TRM doesn't give any more information on what this does, I guess it's a hint to perform a prefetch on both destinations of a conditional branch.