Cyclone Fixes

[Alpha2]

there's always a margin for error but getting close as humanly possible is still a great achveiment. I hope the new version gets a quick and thurough testing!

 

[Reesy]

Thunderforce 4 now has problems

This is probably because the Stop opcode was unfinished (it was not stopping the CPU). It is now fixed, I also missed the fact that Cyclone didn't compile with armasm (Microsoft assembler), so I released another version which fixes that.

I don't think this is 100% core though, it still has some timing and flag problems, but it's moving that direction.

The new version can be found at the same location. Please report any problems if you mess with it.

​

Notaz,

I did make one change to the way you deal with the Stop opcode, I've made it clear the cycles before exiting cyclone when halted. If this is not done then the timing in the emulator will get screwed up.

I've also added irq call back functionality, I've noticed that you just clear the Irq flag but this can interupt problems in emulators. So its best to call back the emulator and let it decide to clear the interupts or not.

You can get my changes here

http://www.angelfire.com/trek/reesy/Cyclonev0.0082.zip

P.S Street Fighter works and Syndicate. Thunder Force 4 is also perfect, nice job

Reesy

 

[notaz]

I've also added irq call back functionality, I've noticed that you just clear the Irq flag but this can interupt problems in emulators. So its best to call back the emulator and let it decide to clear the interupts or not.

Nice, but because of this change Cyclone started crashing under Symbian platform. It appears that CycloneIrqCallback pointer, which you defined in the middle of code, cannot be changed under Symbian, because it marks program code section as read-only. To fix that, I moved that pointer to CPU context, this will also allow different handlers for different CPUs (if more than 1 CPU is emulated).

Also, you were strangely passing SR high as the first parameter for that handler, instead of IRQ level. You probably missed the orr statement above..

So I modified your changes and posted to my site.

 

[Alpha2]

It's like watching a chess match, but both people are on the same side!

 

[Reesy]

I've also added irq call back functionality, I've noticed that you just clear the Irq flag but this can interupt problems in emulators. So its best to call back the emulator and let it decide to clear the interupts or not.

Nice, but because of this change Cyclone started crashing under Symbian platform. It appears that CycloneIrqCallback pointer, which you defined in the middle of code, cannot be changed under Symbian, because it marks program code section as read-only. To fix that, I moved that pointer to CPU context, this will also allow different handlers for different CPUs (if more than 1 CPU is emulated).

Also, you were strangely passing SR high as the first parameter for that handler, instead of IRQ level. You probably missed the orr statement above..

So I modified your changes and posted to my site.

​

Ahh yes thats a much better idea. With regards the SR high parameters, yep it looks like I missed something as I merged my stuff into your code. I only need to pass the current IRQ level to the emulator not the SR flags. Nice spot.

I'll go and grab your latest then, cheers.

Reesy

EDIT - Is there any reason why the callback pointer is added to the end of the cyclone context, I've moved it instead and decreased the padding. This way I don't have to change my save state format.

FROM

struct Cyclone
{
  unsigned int d[8];   // [r7,#0x00]
  unsigned int a[8];   // [r7,#0x20]
  unsigned int pc;     // [r7,#0x40] Memory Base+PC
  unsigned char srh;   // [r7,#0x44] Status Register high (T_S__III)
  unsigned char xc;    // [r7,#0x45] Extend flag (____??X?)
  unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]
  unsigned char irq;   // [r7,#0x47] IRQ level
  unsigned int osp;    // [r7,#0x48] Other Stack Pointer (USP/SSP)
  unsigned int vector; // [r7,#0x4c] IRQ vector (temporary)
  int pad[2];
  int stopped;         // [r7,#0x58] 1 == processor is in stopped state
  int cycles;          // [r7,#0x5c]
  int membase;         // [r7,#0x60] Memory Base (ARM address minus 68000 address)
  unsigned int   (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc
  unsigned char  (*read8  )(unsigned int a);  // [r7,#0x68]
  unsigned short (*read16 )(unsigned int a);  // [r7,#0x6c]
  unsigned int   (*read32 )(unsigned int a);  // [r7,#0x70]
  void (*write8 )(unsigned int a,unsigned char  d); // [r7,#0x74]
  void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]
  void (*write32)(unsigned int a,unsigned int   d); // [r7,#0x7c]
  unsigned char  (*fetch8 )(unsigned int a);  // [r7,#0x80]
  unsigned short (*fetch16)(unsigned int a);  // [r7,#0x84]
  unsigned int   (*fetch32)(unsigned int a);  // [r7,#0x88]
  int (*IrqCallback)(int int_level);          // [r7,#0x8c] - optional irq callback function
};

TO

struct Cyclone
{
  unsigned int d[8];   // [r7,#0x00]
  unsigned int a[8];   // [r7,#0x20]
  unsigned int pc;     // [r7,#0x40] Memory Base+PC
  unsigned char srh;   // [r7,#0x44] Status Register high (T_S__III)
  unsigned char xc;    // [r7,#0x45] Extend flag (____??X?)
  unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]
  unsigned char irq;   // [r7,#0x47] IRQ level
  unsigned int osp;    // [r7,#0x48] Other Stack Pointer (USP/SSP)
  unsigned int vector; // [r7,#0x4c] IRQ vector (temporary)
  int pad1;
  int (*IrqCallback)(int int_level);          // [r7,#0x54] - optional irq callback function
  int stopped;         // [r7,#0x58] 1 == processor is in stopped state
  int cycles;          // [r7,#0x5c]
  int membase;         // [r7,#0x60] Memory Base (ARM address minus 68000 address)
  unsigned int   (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc
  unsigned char  (*read8  )(unsigned int a);  // [r7,#0x68]
  unsigned short (*read16 )(unsigned int a);  // [r7,#0x6c]
  unsigned int   (*read32 )(unsigned int a);  // [r7,#0x70]
  void (*write8 )(unsigned int a,unsigned char  d); // [r7,#0x74]
  void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]
  void (*write32)(unsigned int a,unsigned int   d); // [r7,#0x7c]
  unsigned char  (*fetch8 )(unsigned int a);  // [r7,#0x80]
  unsigned short (*fetch16)(unsigned int a);  // [r7,#0x84]
  unsigned int   (*fetch32)(unsigned int a);  // [r7,#0x88]
  
};

Obviously we don't need to change the main release but you may noticed something different If I ever pass you any more changes, thanks again.

Reesy

 

[Reesy]

Version 0.0084 Released.
+ Merged my flag emulation changes for DIVS, DIVU and all shift opcodes.

I ran version 0.0083 through by debugger that compares Cyclone to Musashi and found that flags were being calculated differently, my aim was to reproduce the exact M68K emulation that Musashi produces.

Cyclone_v0.0084.zip

Later

Reesy

 

[slaanesh]

What's the current status of Cyclone? It seems to be very compatible with most 68K games now.

Have there been any changes/fixes since this release?