(...)BTW, it's slightly more complex than that: cacheable reads are 20% faster, non-cacheable writes are 90% faster (this is very important for framebuffer).
In thread you've shown Mans measured beast-case read bandwidth (PLE+NEON case) as 741113693 B/s = 706.78MB/s
Is this +20% of read bandwidth relative to this case (thus being 848.1MB/s) ?
But back to SGX.
I've started deciphering instructions for SGX 2D engine (it's a separate, dedicated entity for 2D fill/blit operations). And I must say I'm impressed by both design decision and (potential) capabilities of unit.
Separate 2D pipe is very good design decision from power efficiency standpoint. Simple, dedicated 2D blitter does not occupy complex resources of 3D pipes (think tile accelerator, shaders engines), and it should be 'good enough' to perform most tasks required do display OS GUI.
As for capabilities - it can do block fills, pattern fils, 3-parameter raster ops, format conversions (source can be (A)RGB, paletted and even YUV 4:2:2), flip and rotation and many modes
of alpha blending
. Im not sure if this can be exposed in DRI driver framework, though (if somebody knows - PM me). I didn't found any indication that in can do rescaling, so for stretch-blits we'll have to use 3D pipeline... But it still look very good.