Craigix Discloses Information On New Gp2x?


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X-Code said:
I thought that I was the one drinking the beer Julius, a DS type design with widescreens?... eeek! ( only joking take no offence ) :lol:

I do imagine DS emulation feasible... Only need someone capable of coding the emu I guess, as this new system seems to be powerful enough.
As for gp32... rokdcasbah, dunno if that would be possible, but it would be great :)


I'd been wondering about DS emulation as well :p

If it is possible, I guess it's not going to be too likely to appear for a couple of years (if at all) on this new system, as there still aren't any decent PC based emulators that are capable of running at a decent speed on anything below 2GHz with reasonable commercial compatibility.


The main thing I'm wanting to get hold of this system for at the minute is to have a go at using Kismet :ph34r:. I've shown this machine to one of my friends (who is in no way interested in computer games) and they have said they would be buying it if it could run Kismet and other wifi apps. They'd even be willing to spend up to £200 on it :eek:
 
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Aircrack.. :)

Hmm.. Maybe, we could even spawn an entire new hobby..
Warbiking...

Also: someone make a proper Usenet (binaries!) client for it, and make it so that it scans for WLANs in a low-power mode (30mhz?), and once it has found one, connect to it and start downloading....

Borderline illegal and pretty abusive, but at least you'd be able to tell that that stroll throughout town was at least somewhat useful... :p

That reminds me....

Will there be inbuilt storage? I mean not the tiny 64mb (or whatever) we have on the GP2x, but something bigger? 2gb? 1gb? If it's a big high-speedish, could be pretty useful. Then again, SD cards are fine, too. But having 2gb of storage inbuilt will really push a lot more people to make the purchase, I believe!
 
Vimacs said:
We should have fully working DMA now (if MSE isn't stupid) that should also help a lot with streaming things.

A bigger concern than DMA between the SD card interface and Main RAM (as important as that may be), as I view it at any rate, is if the MMSP2+ will be free from internal communication design errors inherent in the MMSP2 (lack of DMA between crucial blocks). If I am not mistaken, a graphical blit to the display required, on the GP2X, that the 920T (Main CPU) copy the image data to be drawn (let's say, a sprite) from one area of Main RAM, to another area of Main RAM that was acting to store a surface to be drawn to the screen. Then the blitter would access this, with data transfer facilitated by the 920T, blit the surface, and again with the aid of the 920T, copy this surface to the framebuffer (which was also in Main RAM) to then be drawn to the display. The requirement of the main CPU to shuttle around data between every component meant it was heavily burdened during any transfer, and use of the hardware blitter made it a middleman. This would indicate using the hardware blitting functionality of the MMSP2 was actually LESS efficient than blitting entirely in software using the 920T alone. If issues like that exist in the MMSP2+, even discrete memory ICs (and paths to said ICs) would only slightly alleviate such issues.

(Such results were repeatably observed in test applications determining the feasibility of the GP2X as a development platform. Use of the hardware blitting functionality provided in the MMSP2, as implemented by the GP2X, resulted in nearly-identical or in many cases dramatically slower performance.)

I'm not sure I've properly communicated this concern. If such an issue still existed, use of 2D/3D acceleration hardware might actually provide NO performance benefit over existing software graphics on the GP2X, meaning the only worthwhile performance gains were essentially that of a higher-clocked processor. Barely any improvement at all, and a lot of wasted money and power. In light of this, the seriousness of such a decision should be evident.

To address comments that my posts are intended to be 'negative' toward the GP2X, Sam Fisher has correctly asserted that my statements are meant with no ill intent and rather to make clear to non-developers and persons involved in the design of any new system shortcomings involved in prior implementations of the MMSP2 in the GP2X design, and how they might be alleviated to produce the best possible result machine. Upon signing up for an account on this forum I did not observe any regulation stating I was not permitted to state that the GP2X or MMSP2 are imperfect designs. As the old wisdom goes, "Those who do not learn from the past are doomed to repeat it". While the GP2X was a very useful machine, it was by no means perfect, and to deny this fact is to state no future device should exist at all, and this thread closed. This does not appear to be a popular opinion.
 
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Esp3tek said:
this model... why not?

gp4Q1.jpg
Looks nice but I think the keyboard lays to deep and the edges at the side of the keyboard are to sharp to be comfortable. The keyboard should rest in higher position, maybe via thinner LCD or the LCD screen/slider is placed a little bit higher than the case of the device. Plus, the corners of the edges should be smoother so you can use the keyboard longer without hurting thumbs. :)

gp4q2lg7.jpg
 
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KeyboardCowboy said:
If I am not mistaken, a graphical blit to the display required, on the GP2X, that the 920T (Main CPU) copy the image data to be drawn (let's say, a sprite) from one area of Main RAM, to another area of Main RAM that was acting to store a surface to be drawn to the screen. Then the blitter would access this, with data transfer facilitated by the 920T, blit the surface, and again with the aid of the 920T, copy this surface to the framebuffer (which was also in Main RAM) to then be drawn to the display.
no
Just have your two buffers in upper mem and change the fb address every loop, this way you have free double buffering and you don't need to blit your whole fb all the time. Also blits can be "free" by using the hardware Blitter.

But lets stop this, this thread isn't about gp2x problems or general bashing, and we all know your opinions more than enough.
So pleas stop dragging this thread off topic now, thanks.
 
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Vimacs, don't even try to argue with him I think we all know what he is starting to do (already). I'm signing off this thread, we will be back in a months time :)
 
ohh iam not sure this was asked is it possbible to emulate the gp32 or to recomplie some gp32 games to make it woirk on this new system.. also could it play gp32 commerical games or was their drm... i never had a gp32...







KeyboardCowboy said:
Vimacs said:
We should have fully working DMA now (if MSE isn't stupid) that should also help a lot with streaming things.

A bigger concern than DMA between the SD card interface and Main RAM (as important as that may be), as I view it at any rate, is if the MMSP2+ will be free from internal communication design errors inherent in the MMSP2 (lack of DMA between crucial blocks). If I am not mistaken, a graphical blit to the display required, on the GP2X, that the 920T (Main CPU) copy the image data to be drawn (let's say, a sprite) from one area of Main RAM, to another area of Main RAM that was acting to store a surface to be drawn to the screen. Then the blitter would access this, with data transfer facilitated by the 920T, blit the surface, and again with the aid of the 920T, copy this surface to the framebuffer (which was also in Main RAM) to then be drawn to the display. The requirement of the main CPU to shuttle around data between every component meant it was heavily burdened during any transfer, and use of the hardware blitter made it a middleman. This would indicate using the hardware blitting functionality of the MMSP2 was actually LESS efficient than blitting entirely in software using the 920T alone. If issues like that exist in the MMSP2+, even discrete memory ICs (and paths to said ICs) would only slightly alleviate such issues.

(Such results were repeatably observed in test applications determining the feasibility of the GP2X as a development platform. Use of the hardware blitting functionality provided in the MMSP2, as implemented by the GP2X, resulted in nearly-identical or in many cases dramatically slower performance.)

I'm not sure I've properly communicated this concern. If such an issue still existed, use of 2D/3D acceleration hardware might actually provide NO performance benefit over existing software graphics on the GP2X, meaning the only worthwhile performance gains were essentially that of a higher-clocked processor. Barely any improvement at all, and a lot of wasted money and power. In light of this, the seriousness of such a decision should be evident.

To address comments that my posts are intended to be 'negative' toward the GP2X, Sam Fisher has correctly asserted that my statements are meant with no ill intent and rather to make clear to non-developers and persons involved in the design of any new system shortcomings involved in prior implementations of the MMSP2 in the GP2X design, and how they might be alleviated to produce the best possible result machine. Upon signing up for an account on this forum I did not observe any regulation stating I was not permitted to state that the GP2X or MMSP2 are imperfect designs. As the old wisdom goes, "Those who do not learn from the past are doomed to repeat it". While the GP2X was a very useful machine, it was by no means perfect, and to deny this fact is to state no future device should exist at all, and this thread closed. This does not appear to be a popular opinion.

it seems to me almost everything you type is like 3 pargraphs and in every other sentence you hint or remark the problems of the gp2x...
 
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craigix said:
Vimacs, don't even try to argue with him I think we all know what he is starting to do (already). I'm signing off this thread, we will be back in a months time :)
Seeya, come back with pics, won't you? :)
 
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Vimacs, whether this is Epi or not, he is entitled to his opinion and isn't flaming. As to what he says it has worth, in fact more than most....
 
I have very little available time, especially to spend arguing with strangers across the internet. So if you feel that is my intent, you are mistaken. It was my sincere hope to have a rational discussion of this matter in a professional tone. Hopefully much behavior I've seen thus far is not indicative of a future trend and won't make me regret my decision to even give this prospective platform a look. Given that I have more patience than most developers likely will, it would be in the best interests of more than oneself.
 
KeyboardCowboy said:
If I am not mistaken, a graphical blit to the display required, on the GP2X, that the 920T (Main CPU) copy the image data to be drawn (let's say, a sprite) from one area of Main RAM, to another area of Main RAM that was acting to store a surface to be drawn to the screen.
That would not be necessary. It would be more normal to store the sprite in that "other area" normally rather than copying it there when needed. That "other area" is just the upper 32 megs of memory which is not managed by Linux (a software decision).
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Then the blitter would access this, with data transfer facilitated by the 920T,


Not really facilitated by except that the 920T does have to say "go" to the blitter.
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blit the surface, and again with the aid of the 920T, copy this surface to the framebuffer (which was also in Main RAM) to then be drawn to the display.


Again, you could do it this way, but that would be a software organization decision. It would be more normal to blit directly to the back buffer, stored in "upper" memory.

Highly-optimized assembly code can basically equal the blitter's performance for simple copies (which is what most people do), but there is still a benefit to using the blitter because you can do other computations while waiting for the blitter to finish (though you might want to try running from the cache because the memory bus will be busy).

They (by which i mean the firmware developers) decided to make the upper 32mb uncached, which is why it can get uncomfortable to use frame buffers stored there and programs often do store their frame buffers in the lower 32 mb if they access it in more complex ways than just blitting to it. This is all for software and system configuration reasons. The famous "MMU Hack" does not get around a MMSP2 limitation, it changes the caching behavior, making general access to that memory able to benefit from cacheing.

The linux implementation could make some interesting performance improvements if it wanted, by offering ioctls to change the cache status of "video" memory regions including the frame buffer. I don't know if this is being worked on, but it is not a hack designed to deal with bad hardware, it's just thinking about how to deal with the fact that user processes see virtual address spaces managed by linux, but hardware like the blitter see physical addresses. Another interesting facility that could be built into the kernel would be the ability to 'malloc' a chunk of lower memory that was guaranteed contiguous and at a fixed physical address. Such memory blocks could then be used by other hardware components. But again, that has nothing to do with the MMSP2 per se.
 
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If that's the case, the issue of hardware blitting being the same speed, or slower than, software blitting is likely the result of contention across the bus. Hopefully any new machine wouldn't make the same mistake of putting so many bandwidth-hungry components on the same path to a shared pool of SDRAM again.

Even with the use of Mobile DDR memory, a shared memory pool is a poor idea at best. I would view the only rational choice as dividing up RAM into 3 separate banks, for each CPU core and one entirely dedicated to graphics use. (Or, in the case of using the 3D hardware as a VFPU, a general purpose block of RAM.)
 
craigix said:
Vimacs, don't even try to argue with him I think we all know what he is starting to do (already). I'm signing off this thread, we will be back in a months time :)
Argh, I hate you epicentre, look what you've done now!

Craig, if you read this, take a look at my dpad design. I think it could work, if you are looking for a nice plain old pad.


Good luck with the project guys, I know whatever you do, you'll make us proud.
 
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Lighten up people. I don't understand why everyone has to be so defensive. We're not at war are we? Anyway, I have nothing more to say on this matter so I'll just post another image. I played around some more in Photoshop and I think a white unit could look pretty cool too (regardless of design ;)).

whitedp9.jpg
 
KeyboardCowboy said:
If that's the case, the issue of hardware blitting being the same speed, or slower than, software blitting is likely the result of contention across the bus. Hopefully any new machine wouldn't make the same mistake of putting so many bandwidth-hungry components on the same path to a shared pool of SDRAM again.
Yes, the slow shared memory combined with the small caches is the major performance bottleneck on the gp2x and the reason it is difficult to put the 940T to work effectively in applications that are already pushing the bandwidth limits.
 
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KeyboardCowboy, no one minds you voicing your opinion here or saying what you think, but slagging off a chipset with complete bullshit is just not on. At least get your facts right first.

Since we all know where this is going, I'm unsubscribing from this thread, so don't expect me to argue with you (or anyone else for that matter).
 
Eolair said:
Lighten up people. I don't understand why everyone has to be so defensive. We're not at war are we? Anyway, I have nothing more to say on this matter so I'll just post another image. I played around some more in Photoshop and I think a white unit could look pretty cool too (regardless of design ;)).

whitedp9.jpg
only thing i dont like is that dpad like thing...
 
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QUOTE

only thing i dont like is that dpad like thing...



Yeah, I'm not too sure about that either. I was mostly just trying to avoid showing the patented Nintendo cross ;)

Edit: awful spelling
 
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