Our New Machine, Pandora

[Exophase]

QUOTE
I think that a 600+ MHZ Arm Cortex A8 beats a 200MHZ SH-4 by a large margin. That's just my guess, though.
The 200mhz SH-4 is a RISC (reduced instruction set) processor and was pretty crazy when it was released (1998). Its very optimised for doing a set of specialised instructions. For instance it can multiply two 4x4 matrices in a single cycle, very useful for 3d transformations. Its also superscaler (like the ARM) so it can process >2 instructions per cycle.... not to mention its also got a pretty hefty FPU.

The ARM might be better, but the difference between them (in a gaming sense) isn't as much as you think.

Edit: Made more read-able.

No, I'm going to have to go with Adventus's comment. SH4 wasn't all that "crazy" for when it was released, yeah it was RISC but so is almost anything else released after 1993 (aside from x86 of course). It only has a small handful of vector instructions - I agree that they're optimized for speed (at the expense of accuracy) but what you're saying is crazy. It can do a 4-wide inner product in one cycle, and a vector * matrix transform in 4 cycles; multiplying two 4x4 matrices would take 16 cycles (so you were WAY off). Neon (which is available in Cortex-A8) has a VMLA instruction which does the same thing. Honestly I'm not sure how to read the cycle timings for it but I do know that it's pipelined so as long as you don't need the results immediately (and in 3D code you should be able to do a lot of transformations in parallel) you can probably get a pretty high throughput.

And yeah, SH4 is superscalar, but definitely not more than 2 instructions at a time (it is described as a strictly 2-issue CPU). More than that, you can only pair instructions from the same group (so it has no redundant execution units). Cortex-A8 is also 2-issue but it has two ALUs so you'll probably be able to pair more instructions. Also, ARM is just a much more robust and powerful instruction set than what SH4 uses. SH4 had the advantage of code density but Thumb-2 basically solves that as well. And the Dreamcast's SH4 has less L1 cache (8/16 vs 32/32, as far as I'm aware) and no L2 cache (if proper L2 cache is used a miss from L1 that hits in L2 will only cost 9 cycles on Cortex... I expect the OMAP3430 to have 128KB of L2 cache, I think that's a pretty standard amount).

SH4 might have a clock for clock advantage doing vector transforms, but that doesn't really matter outside of emulating things because OMAP3430 has a video chipset with shaders. And I think in every other category it's worse clock for clock. Now compare it to a Cortex which is clocked at least 3x as high (and perhaps as much as 5x as high) and you don't just have a CPU that's slightly better, you have one that beats the crap out of it.

 

[Adventus]

Well i found it quite quite impressive at the time. XD. I mean it seemed to compete with the PCs at the time. Obviously im not gonna argue with that. Im sure i have no idea, thanks for correcting me. I would dearly like you to prove me wrong though and make me a DC emu.

Yea i guess i misinterpretted some of this information (I guess ill just quote it instead of trying to get my feeble to interpret it): http://www.embedded.com/1999/9903/9903bits.htm
QUOTE
Hitachi’s newest generation of SH-4 chips (of which the SH7750 is the first example) includes a stunningly impressive matrix-transformation instruction. With a single instruction, the SH7750 can multiply a 4x4-element matrix with a four-element array, to produce a new four-element array. In one clock cycle. At 200MHz. And all of the numbers are single-precision IEEE floating-point values. I don’t think there’s another computer in the world, regardless of price, that can perform that function so quickly. It slings 288 bits of data around inside the chip every cycle (eight 32-bit elements, plus a 32-bit sum). It’s no wonder that Sega chose the SH7750 as the processor for its Dreamcast video game console.

So it can do a 4x4 matrix multiplied by a 4x1 in one clock cycle? does that mean a 4x4 times 4x4 in four cycles?

and: http://www.segatech.com/technical/cpu/index.html
QUOTE
The figure (above, right) shows a better example of what the SH-4's floating point hardware can accomplish. Here the back register file is loaded with 16 values and the hardware performs the following matrix operation in seven clock cycles:

f0*b0 + f1*b1 + f2*b2 + f3*b3 ' f0
f0*b4 + f1*b5 + f2*b6 + f3*b7 ' f1
f0*b8 + f1*b9 + f2*b10 + f3*b11 ' f2
f0*b12 + f1*b13 + f2*b14 + f3*b15 ' f3

The SH-4 is fully pipelined, and the RISC architecture can repeat these 16 fmuls and 12 fadds (28 operations) every four clock cycles, for an average of seven floating point operations per cycle. The superscalar CPU and double-precision fmov allow registers to be loaded from, and stored to cache during these four cycles, so the operations are sustainable. At its 200-MHz clock speed, the SH-4 achieves 1.4-GFlops performance, sustained.
I dont doubt the A8 isnt an extremely powerful CPU for general purpose stuff and more powerful than a SH-4, but i was discussing it from the perspective of emulation.... considering the level of specialisation, im just unsure how well mapping a SH-4 would work out.

Wouldnt the relative floating point performance be a deciding factor in DC emu?

 

[Exophase]

Well i found it quite quite impressive at the time. XD. I mean it seemed to compete with the PCs at the time. Obviously im not gonna argue with that. Im sure i have no idea, thanks for correcting me. I would dearly like you to prove me wrong though and make me a DC emu.

Yea i guess i misinterpretted some of this information (I guess ill just quote it instead of trying to get my feeble to interpret it): http://www.embedded.com/1999/9903/9903bits.htm
QUOTE
Hitachi’s newest generation of SH-4 chips (of which the SH7750 is the first example) includes a stunningly impressive matrix-transformation instruction. With a single instruction, the SH7750 can multiply a 4x4-element matrix with a four-element array, to produce a new four-element array. In one clock cycle. At 200MHz. And all of the numbers are single-precision IEEE floating-point values. I don’t think there’s another computer in the world, regardless of price, that can perform that function so quickly. It slings 288 bits of data around inside the chip every cycle (eight 32-bit elements, plus a 32-bit sum). It’s no wonder that Sega chose the SH7750 as the processor for its Dreamcast video game console.

So it can do a 4x4 matrix multiplied by a 4x1 in one clock cycle? does that mean a 4x4 times 4x4 in four cycles?

No. It can do it in a single instruction. That instruction takes 4 cycles. The information that it takes 1 cycle is dead wrong (and it's a shame because he decorated that point so much...). The vector inner product takes one cycle, and the matrix transform is like four of those. And the article you quoted has a lot of kinda weak and self defeating arguments in general, IMO >_>

and: http://www.segatech.com/technical/cpu/index.html
QUOTE
The figure (above, right) shows a better example of what the SH-4's floating point hardware can accomplish. Here the back register file is loaded with 16 values and the hardware performs the following matrix operation in seven clock cycles:

f0*b0 + f1*b1 + f2*b2 + f3*b3 ' f0
f0*b4 + f1*b5 + f2*b6 + f3*b7 ' f1
f0*b8 + f1*b9 + f2*b10 + f3*b11 ' f2
f0*b12 + f1*b13 + f2*b14 + f3*b15 ' f3

The SH-4 is fully pipelined, and the RISC architecture can repeat these 16 fmuls and 12 fadds (28 operations) every four clock cycles, for an average of seven floating point operations per cycle. The superscalar CPU and double-precision fmov allow registers to be loaded from, and stored to cache during these four cycles, so the operations are sustainable. At its 200-MHz clock speed, the SH-4 achieves 1.4-GFlops performance, sustained.


Yes, as it said, four clock cycles, NOT one. Now you see where it gets seven FLOPs per cycle, it's one FMUL and three FMACs (which they're counting as two operations each, a multiply and an addition) to do a dot product. That's why Hitachi promotes it as 1.4 GFLOPs a second. Which is kinda an inflated number when you think about it.

I dont doubt the A8 isnt an extremely powerful CPU for general purpose stuff and more powerful than a SH-4, but i was discussing it from the perspective of emulation.... considering the level of specialisation, im just unsure how well mapping a SH-4 would work out.

The thing is that VFPU instructions like this are not uncommon anymore, they just stand out on the SH4 because aside from dot product and vector transform it doesn't have any vector instructions at all (which makes it far less useful for more general purpose packed operations). Like I said, Neon can do a dot product in one instruction too. It might not be as fast (although it might be able to sustain a rate of one per cycle when they're overlapped), and it might take 4 of them to do transformation (which is not really a big deal), but it can do still do them and probably with higher precision than SH4 does.

Wouldnt the relative floating point performance be a deciding factor in DC emu?

I was never arguing for DC emulation in the first place. I was more unhappy with your comment that the Cortex CPU will only be a little more powerful the Dreamcast. It takes so much more power to emulate most of the time that I don't really see it happening, but that doesn't mean that a 600MHz-1GHz Cortex isn't in an entirely different class.

EDIT: Another thing that I found about the SH4 that really sucks is that the cache is direct mapped. That's the same as saying one way set associative. For general purpose code you're liable to end up with way collisions all over the place.

 

[atomicthumbs]

QUOTE
I think that a 600+ MHZ Arm Cortex A8 beats a 200MHZ SH-4 by a large margin. That's just my guess, though.

The 200mhz SH-4 is a RISC (reduced instruction set) processor

Yeah, so's the ARM. ARM originally stood for Advanced RISC Machines.

 

[Orkie]

Yeah, so's the ARM. ARM at one time stood for Advanced RISC Machines, originally standing for Acorn RISC Machine.

 

[craigix]

We should have some more video and extra information soon, just getting all the F200 packages ready for shipping etc. for a couple of days.

 

[X-Code]

Waits for new info whilst working on arcade cabinet repair / restoration / modification B)


Edit: Oh what fun! :lol:

 

[sam fisher]

We should have some more video and extra information soon, just getting all the F200 packages ready for shipping etc. for a couple of days.

Cool. I really really want one of these

 

[Vorporeal]

We should have some more video and extra information soon, just getting all the F200 packages ready for shipping etc. for a couple of days.

I'm going to assume these packages are pre-ordered F200s, not the packages that he was going to send to people who donated to his run thingy... :blink:

 

[atomicthumbs]

We should have some more video and extra information soon, just getting all the F200 packages ready for shipping etc. for a couple of days.

 

[Adventus]

QUOTE
No. It can do it in a single instruction. That instruction takes 4 cycles. The information that it takes 1 cycle is dead wrong (and it's a shame because he decorated that point so much...). The vector inner product takes one cycle, and the matrix transform is like four of those. And the article you quoted has a lot of kinda weak and self defeating arguments in general, IMO >_>
Yea just realised the article contradicts itself. It kind of threw me off balance because of how excited he was. Followed up with the segatech propergander it was a deadly concoction.

QUOTE
More than that, you can only pair instructions from the same group (so it has no redundant execution units).
I though it was the opposite, it can simultaneously do two instructions from different groups?

I guess i was kind of banking on the A-8's lack of an FPU, but from what you've said it seems the Neon/VFP can easily take its place.

 

[realyst]

We should have some more video and extra information soon, just getting all the F200 packages ready for shipping etc. for a couple of days.

I'm going to assume these packages are pre-ordered F200s, not the packages that he was going to send to people who donated to his run thingy... :blink:



Yes, he's going to send out 250$ consoles to all those who made a minimum donation of 5$..... ¬_¬

 

[Exophase]

I though it was the opposite, it can simultaneously do two instructions from different groups?

Yeah, that's what I meant >_> Cortex-A8 has more parallelism.

I guess i was kind of banking on the A-8's lack of an FPU, but from what you've said it seems the Neon/VFP can easily take its place.

Neon is actually far more versatile in general, it can do all sorts of things (for vector, not just scalar floating point). The registers are also more accessible (not split over two banks). Where did you get the idea that Cortex-A8 doesn't have an FPU..? It even has IEEE double precision support, although it's slow (not pipelined).

 

[Adventus]

QUOTE
Neon is actually far more versatile in general, it can do all sorts of things (for vector, not just scalar floating point). The registers are also more accessible (not split over two banks). Where did you get the idea that Cortex-A8 doesn't have an FPU..? It even has IEEE double precision support, although it's slow (not pipelined).
Well one of the "big features" of the Cortex A-9 is that its got a FPU and a Neon, i kind of assumed this was because the A-8's neon didnt have similar functionality/speed of a dedicated FPU. I've struggled to find any hard information on the actual performance of the VFP.

Edit: The PSP also has both a VFP and FPU.... i guess i took this as an indication that a VFP by its self woudn't suffice.

 

[StealthBagel]

While the possibilities for emulation are impressive and this handheld will open the door to emulation of 3D systems at full speed, I'm more interested two things.... how polished existing 2D system emulation can become; no more 'full speed' that is really 3x frameskip (not full speed at all), instead 60fps all around on the major 8 and 16-bit platforms.

And number 2, regardless of if the handheld successfully emulates the dreamcast or equal ridiculousness, what incredible things can be done with a 500 MHz+ ARM core, a true powerful GPU, a properly made chipset without major bottlenecks, DDR memory, and controls that aren't terrible. The possibilities for very high end 2D are stunning and I can only hope there will be some good demonstrations of the OMAP3430's power in this handheld..... with gp2x most homebrew never used 10% of the capability that was there. There was some really respectable stuff like Vektar but just not enough of it....

I know I'll be doing my part to tap the true power of this chipset and hopefully the handheld is a suitably stable, comfortable and reliable vessel to deliver that capability to software..... a big problem w/ gp2x was a lot of CPU power and appreciable graphics capability and often no way to take full advantage of it... or if you did something like controls or battery life got in your way.

 

[Adventus]

There are plenty of really good homebrew (and even more shithouse ones) "higher level" game designers and programmers, look at the success of XNA and GameMaker. These are the people that seem to be lacking in the GP2X community, we have some very talented low level programmers making ports and emulators.... but to design an original game you often need some one of a different orientation..... (hmmm that sounded bad, probably just my perverse mind).....

Platforms like the GP2X, scare them off when they realise to get decent performance they have to actually interact with the hardware to some extent instead of interfacing through a standardised API. Their wouldn't be many game programmers willing to write a software rasteriser. I think that the craiganator's compliance with OpenGL 2.0 and SM3.0 will make development of good original Homebrew games much more a reality. Especially since most apps written and techniques developed on PC will translate across. Additionally, The increased CPU power will make the overhead of standardised libraries less of a problem.

Personally i am of the OGL graphical whoring orientation (funny since im much more a RETRO fan) and am currently working my way down, so alot of this stuff is still fairly new to me.

 

[atomicthumbs]

There are plenty of really good homebrew (and even more shithouse ones) "higher level" game designers and programmers, look at the success of XNA and GameMaker. These are the people that seem to be lacking in the GP2X community, we have some very talented low level programmers making ports and emulators.... but to design an original game you often need some one of a different orientation..... (hmmm that sounded bad, probably just my perverse mind).....

Platforms like the GP2X, scare them off when they realise to get decent performance they have to actually interact with the hardware to some extent instead of interfacing through a standardised API. Their wouldn't be many game programmers willing to write a software rasteriser. I think that the craiganator's compliance with OpenGL 2.0 and SM3.0 will make development of good original Homebrew games much more a reality. Especially since most apps written and techniques developed on PC will translate across. Additionally, The increased CPU power will make the overhead of standardised libraries less of a problem.

Personally i am of the OGL graphical whoring orientation (funny since im much more a RETRO fan) and am currently working my way down, so alot of this stuff is still fairly new to me.

Well, there is Game Editor, which is like Game Maker and can output for GP2X.

 

[fusion_power]

. with gp2x most homebrew never used 10% of the capability that was there. There was some really respectable stuff like Vektar but just not enough of it....

I think, as more powerful a machine is, as more unoptimized Software is produced for it, because everything can be done just with pure CPU Power. This is so with PC's and often enough with Consoles, especially Homebrew.
Ok, this strathegy is no problem until an mobile Device comes into play. Because here counts the battery power to and as more CPU power we can save, as longer we can play mobile. So I hope the new handheld is easy to use for coders, which means simple access to all the hardware-accelerated features instead of pure software simulation of "whatever"...
Yes, I have no doubt that we can have Full-Speed SNES, GBA etc...
The question is, are people happy with it with unoptimized Software -Acceleration at 550MHz or with Hardware Optimized coding for maybe only 250-300MHz and longer battery life? ^^"""
I'm not a coder but I really hope, the Handheld makes it easy to use all of its Hardware powered Chipset Features more easy than the GP2X does.

 

[pupnik]

The question is, are people happy with it with unoptimized Software -Acceleration at 550MHz or with Hardware Optimized coding for maybe only 250-300MHz and longer battery life? ^^"""
I'm not a coder but I really hope, the Handheld makes it easy to use all of its Hardware powered Chipset Features more easy than the GP2X does.

A lot of straight compiles of linux sdl homebrew games don't run well on a 225mhz ARM9 with 64MB but run fairly well on a 333mhz ARM11 with 128MB

You're right, having 800x480, decent CPU and standard linux will make compiles of a lot of linux games simpler. Like... anything on http://pupnik.de/software.

It opens up a lot of win for not much work.

 

[Lazy8s]

When the OMAP2s were introduced in phones in 2005, they clocked the CPU at most to TI's stated standard of 330 MHz, and a lot of devices actually had them with a clock rate well under that. The corresponding clock rate for the MBX GPU is set at around 55 MHz.

OMAP3430 will probably come in at around 550 MHz for the ARM Cortex as stated, and the SGX GPU might correspond at 110 MHz as these chips are mainly aimed at phones.

That speed would put this new machine's graphics performance at about half of what PowerVR lists on their site since they're considering for 200 MHz.

Of note, however, is that a more recent OMAP2420 device, the Nokia N810, runs the SoC faster with the ARM core at 400 MHz.