I absolutely plan to use the M4s. My company writes software for M4 cores and I'm hoping to convince my boss that it'd be worthwhile to have it running on an OMAP5 board as a demonstration. Once I'm paid to learn how to use them I won't feel like a shit trying to do it in my free time and I may actually come up with something useful. That's my hypothesis anyway, we'll see how it works in practice once I've actually got a Pyra.
Ah yes, something useful. That is the problem - similiar to DSP on Pandora.
But even knowing how to run code on the M4 cores will be a step forward so good luck with that.
I personally have experience with baremetal programming on a DM8148, which includes the dual-cortex-M3 predecessor (Ducati) to the dual-cortex-M4 subsystem (Benelli). Apart from the cores used the subsystems are identical afaik.
My experience is that it's really easy to at least put one core to use. There's a weird little MMU ("AMMU") integrated into the Unicache that should be setup properly, although the reset defaults are already usable and in particular map address 0 to the local SRAM of the subsystem. This means that firing it up is a simple matter of:
- Release subsystem from reset
- Upload code to subsystem SRAM, adjust AMMU settings to taste
- Release core from reset
And it's up and running! Putting both cores to work is slightly more interesting since, apart from their Private Peripheral Bus, the cores have identical views of the address space. Neither AMMU nor the L2 MMU has the ability to distinguish between the two cores. This means that you effectively have to program them as if they're two threads in a single process, which is slightly annoying.
I used the DSP for real-time audio processing (no DMA, no rx fifo, max 1 sample per channel buffered in the tx fifo), but the DM814x has a proper C674x DSP. I'm not sure what to make of that bastard child Tesla that's on the omap4 and omap5, or what motivated TI to cut a C64x+ core in half and glue it onto another (but differently configured) instance of that weird AMMU/Unicache IP block instead of the usual GEM/CorePac. It certainly won't help that the current version (v8) of TI's C6x compiler dropped support for Tesla as being "obsolete", and there's (afaik) no published instruction set manual, although it probably wouldn't be very difficult to figure it out.
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Sounds great, do you have already any ideas about possible usecases ?
Note BTW that the subsystem is also closely associated with the camera subsystem (ISS). I don't know if Pyra intends to use it, but if so then you may want to use an M4 core to look after it.