Adventus said:
Assuming the A8's Neon unit is comparable to the SH-4's VFPU.
If by "VFPU" you mean "dot product instruction", and clock for clock Cortex-A8's NEON really isn't comparable since the ops are only 2-way at a time. Using VMLA as the comparable instruction, although it's not really the same it should be if you order your data structures right. VMLA takes two cycles, assuming no data hazards, and I believe the comparable instruction for SH4 takes 1 cycle. This is throughput, not latency, but for things you want to do a bunch of dot products on it's usually easy to parallelize a bunch of them together. So at the same clock speed SH4 wins for this, at 600MHz Cortex-A8 has a marked advantage, and at 900MHz it should be over 2x.
But for applications where performance means more than dot products (which is probably the case for most things we'll be doing), IE integer performance, Cortex-A8 easily beats SH4 even at the same clock speed, so I'm expecting more than 3x the performance at 600MHz. Especially where integer SIMD can be employed on NEON.
Yes, that's very important about the 900 MHZ. From what we've been told, all parts can do 900 MHZ stable, some even higher. If it only eats more battery, I think a lot will gladly make the sacrifice for better emu performance.
