As for the ScO: Last sparc of hope I got these days: RiscV.
So maybe keeping one Pyra in the hope of a RiscV board or similar? I think about that.
It may be I didn't explained RISC-V problem good enough, so I will try one more:
1/ ISA vs implementations
RISC-V "ISA" is a very good thing because it is OPEN, but the OPEN part is the ISA, the instruction set. And the ISA (Instruction Set Architecture) is only an ABSTRACT MODEL of an architecture and instructions of a processor. You need an implementation of that ISA in real hardware, and for the same ISA can be infinite implementations and very very different implementations.
If you look for example at an specific ISA, for example IA-32 (Intel Architecture 32 bits), i.e. 32-bit x86 ISA (the one we used in IBM PC compatibles time ago), you will find even inside Intel there are very different implementations for that ISA. For example an Intel 386 is very different internally from an Intel 486 or an original Pentium, or Pentium 4 or Pentium M. All of them (forgetting some extensions and some minor instruction added) execute the same ISA, they get the same final results with same instructions, but they do it in very different ways internally and with very different performance results. If you could look inside internal specific CPU, you would see very different things, although all them run same ISA.
Let's go back to RISC-V: ISA (abstract model) is OPEN, but most implementations of that ISA, near all different, will be totally closed, like black boxes, and near all commercial implementations will be closed.
Of course there are and there will be open design of RISC-V ISA implementations, but most of them are/will be low-performance and won't get to real silicon masks, usually they are run on FPGA because can't accede to real custom silicon, which is much more expensive for small quantities. And the problem is that FPGA are expensive on performance, consume much more power than custom silicon, and much worse, they have lots of closed parts inside: There is no OPEN FPGA, so if you use an FPGA you end with a custom closed hardware.
So likely with RISC-V you have an open ISA, but you end with a closed commercial implementation on your processor/core (or using a closed FPGA not suitable for a lot of uses where you need better performance, lower power consumption or smaller size).
2/ CPU vs SOC
A SOC includes much more components than only a CPU (or some number of CPU). For example it can include GPU, ISP (image signal processors), DSP, etc, etc. On Pyra you need a GPU/etc/etc, it can't run on a RISC-V SOC without GPU (it would need an external GPU chip, if you found it, being the result bigger in size).
The problem is that most of that components are closed, even some of them use closed drivers and blobs.
What is the point of "I have a RISC-V" if you end with a closed implementation of that ISA inside a SOC with closed GPU/etc/etc with closed drivers, no open complete doc/specifications, blobs...?
The REAL GOOD POINTS for OPEN SOFT is to have total specifications/documentation, good documentation and support, and OPEN DRIVERS. For example NXP is very good in those points, while you can find some RISC-V SOC and boards today bad on all points, even RISC-V without mainline Linux kernel.
3/ There are other OPEN ISA around.
RISC-V will be very important, of course, even with time it could be bigger than ARM, but there has been and there are other OPEN ISA. Even some old ISA become OPEN time ago. For example I cited OpenPOWER used by actual Libre-SOC (they started using RISC-V but changed to POWER because they didn't liked un-open process of RISC-V Foundation).
The point is: if an ISA is OPEN it doesn't mean that a processor using that ISA be OPEN. In fact most of them are closed.
Most RISC-V chips will be used as processors in places where you don't know with it or even where most people doesn't know there is a processor. For example inside a hard-disk, SSD, mouses, routers, IoT, auxiliary processor inside boards...
4/ Is RISC-V bad thing?
No, of course. It is a very good thing, but we must know an OPEN ISA doesn't imply the same than an OPEN OS (like Linux for example).
Someone can design or modify an open OS and run it on actual hardware. But with CPU someone design around ISA, the problem is that you can't run it in real custom silicon: in best case you can run it on an simulator or in an expensive closed FPGA, if that FPGA is big enough to accommodate that CPU design implementation, and with limited speed compared to the speed it could reach on real custom silicon.
5/ RISC-V open model
RISC-V is SO OPEN all can do what they want (they don't need permission). A company can get OPEN RISC-V and make a TOTALLY CLOSED DESIGN. And in fact most RISC-V design will be totally closed. Even they can modify RISC-V ISA or implement custom instructions as they want (even without documenting it to other people).
Don't get wrong: RISC-V is mainly open for manufactures so they can do what they want without having to go open or grant permission; Near all they design and implementations will be closed. In other way they won't use RISC-V.
Behind RISC-V Foundation is not people like Stallman (GNU) or Torvalds (Linux), but the big industry. You can look at RISC-V Foundation members: it is IT industry. They want an Open ISA so they can do what they want without permission/license.
6/ Future RISC-V SOC
Of course, it is likely some future day there will be some good RISC-V SOC from companies doing a good work, like NXP (even NXP will have RISC-V SOC). Even it is possible some company make "very open" SOC with RISC-V inside (also you need availability, good documentation and support). But the problem is that that is hypothetical future. That can take years at best.
And Pyra, with its
slow progress, needs long term availability hard and good support. It is difficult a novel start-up SOC company can warrant long term availability and support.
7/ I LIKE RISC-V too
Don't get me wrong: I like open ISA, all of them, and more the ones getting real silicon and
being successful like RISC-V will be, but being an open ISA isn't equal to having an open SOC or open drivers/etc.
Even I love someone can design a RISC-V implementation on academic environment (there are someone), even in his home, but most of theses will no emerge to us, most of them will go no further than FPGA (being actual FPGA closed hardware).
But I prefer my loved HP 48 series (with "rare" HP Saturn CPU designed and only used by HP). All those calculators are real pocket personal computers, as they can run programs written in assembly/machine language.
