Zii

[OrR]

A site Craig recommended via Twitter:
http://www.zii.com/
Check out this video, it's hilarious:
http://www.zii.com/Technology/StemCell.aspx
Magic chip morphing! 100 times greener at 1/100 the cost! Are they serious or is this some kind of witty joke?!

Edit: It's even recession friendly!

 

[Tag5]

If this is legit then man what a cool little handheld.

 

[OrR]

"This signifies an integral part of our new strategy moving forward to engage every party in a win-win-win partnership."

This HAS to be satire, right? :unsure:
Maybe it's a scam like the Gizmondo?
Somehow the naive buzzword bullshit bingo on the site makes me actually want to buy one of these things... I hope Craig stocks the 0 GB version... Who wouldn't want to own a device called zee Zii EGG? Running on Plaszma? With StemCells? It even has CODECs!

 

[Jourdy288]

I noticed, I wondered how much of this was for real... It didn't seem to have much meaning, and is it true that processors have certain parts for certain functions? I think not.

 

[arrrgh]

"This signifies an integral part of our new strategy moving forward to engage every party in a win-win-win partnership."

The Pointy-Haired Boss would be proud.

 

[Exophase]

It isn't a joke, but I'll be damned if I have the faintest idea as to what it is. The worst part is that they're actually selling them now, no longer just hyping them to death. I'm not enticed to buy something when they won't tell me the first thing about what it actually does beforehand. Is it an FPGA? Is it an area of DSP like processors? Is it an FPGA with DSP slices? Is it a bunch of vector processors? The language they use suggests that it can be any of these things or something else entirely.

I also think their choice of two ARM9s can't possibly make sense. One, I can understand, but why two very outdated CPUs when you're supposed to have this big grid array of heavy lifting stuff? Would much rather have a newer, better, faster ARM than two of those (not that I even know the clockspeed).

Props to first person to give better information on this.

 

[Chip]

Is it an FPGA? Is it an area of DSP like processors? Is it an FPGA with DSP slices? Is it a bunch of vector processors? The language they use suggests that it can be any of these things or something else entirely.

I also think their choice of two ARM9s can't possibly make sense. One, I can understand, but why two very outdated CPUs when you're supposed to have this big grid array of heavy lifting stuff? Would much rather have a newer, better, faster ARM than two of those (not that I even know the clockspeed).

Does this help? They've killed most of the technical pages on their site, but the links in google cache still work.

 

[WarmFluffyUK]

I would prefer one of these

Pomegranate Phone

:lol:

 

[OrR]

The most detailed technical document I could find was this: http://www.zii.com/resource/zms/ziilabs_zms05_datasheet_28JAN09.pdf It's linked from here: http://www.zii.com/Technology/ResourceLibrary.aspx
The most interesting part as far as I can tell:

Media Processing Array - Architecture
 High compute density SIMD architecture
 24 Processing Elements (PE) in 3 clusters
 Each cluster runs the same or independent code
 Multiple High bandwidth memory paths
 Advanced hierarchical cache structure
 Random access to memory per PE
 Shared access to ARM memory
 Independent DMA controller per cluster
 Integer, IEEE 32-bit and 16-bit floating point
 Pre-emptive task switching
 Independent frequency scaling
 Independent voltage domain

Doesn't tell me much, though. Here is a more detailed block diagram:
http://www.ziilabs.com/products/processors/zms05.aspx

 

[Exophase]

I have seen those descriptions, and no, they do not help (and seems to contradict some other things). But I suppose this makes it sound like Cell.

 

[gruso]

They've got viral spam teams in action, they hit the comments on the community Pandora blog ("This is power!! w.zii.com"). GGF, no time to look, busy buying WoW gold.

 

[craigix]

It is really weird isn't it. Probably FPGA and buzz words. I'm trying to obtain one.

 

[tutut]

Introduction :

Game demo (few seconds):

 

[Username]

Looks interesting.

 

[Nova]

This thing is made by Creative, if you didn't already know. (it's not evident on the site)

 

[Exophase]

Wow, they've managed to make a machine that perfectly emulates the experience of playing any one of hundreds of those kinds of games on an iPhone.

Revolutionary.

 

[atiflz]

From what I understand, it is not an FPGA, but a CPU with 24 parallel processing elements, connected by a simple network-on-chip. You may think of PEs as very simple CPUs. They don't have their own pipeline or dedicated cache memories, but share a common cache. It is flexible indeed, but very hard to program(at least hard to optimize) unless they have incredibly smart compilers. The concept is not new but not very common in commercial world.
Intel tried to do it with something like this:

 

[Exophase]

From what I understand, it is not an FPGA, but a CPU with 24 parallel processing elements, connected by a simple network-on-chip. You may think of PEs as very simple CPUs. They don't have their own pipeline or dedicated cache memories, but share a common cache. It is flexible indeed, but very hard to program(at least hard to optimize) unless they have incredibly smart compilers. The concept is not new but not very common in commercial world.
Intel tried to do it with something like this:

"Don't have their own pipeline"? What does that mean? I doubt there have compilers that can parallelize code across cores, no matter how smart.

I've read white paper blurbs that suggest what you're saying, but I've also read other ones that suggest FPGA-like stuff (like being "reprogrammable", why even mention that for something like what you're saying.. I don't know)

I wouldn't say it's not common in the commercial world, every new 3D card out there has a much more massive network of shaders that's basically what you're describing.

From what I understand, this chip has to use those PEs to perform all 3D rasterizing with zero texture fetch in hardware, so I would think for good 3D performance you have to spend a lot of the available resources. If it's setup this way.

 

[atiflz]

"Don't have their own pipeline"? What does that mean? I doubt there have compilers that can parallelize code across cores, no matter how smart.

I've read white paper blurbs that suggest what you're saying, but I've also read other ones that suggest FPGA-like stuff (like being "reprogrammable", why even mention that for something like what you're saying.. I don't know)

I wouldn't say it's not common in the commercial world, every new 3D card out there has a much more massive network of shaders that's basically what you're describing.

From what I understand, this chip has to use those PEs to perform all 3D rasterizing with zero texture fetch in hardware, so I would think for good 3D performance you have to spend a lot of the available resources. If it's setup this way.

"Reconfigurable" is more of buzzword to draw attention. It says so because these PEs can work independently, not in a classic SIMD way. It is indeed somehow similar to GPU architectures, having loads of PE running in parallel. Those simple PEs are usually implemented without pipeline, but you can implement pipelines in software(assigning multiplication and addition to different PEs in something like "return a*b+c").
There won't be any compiler to simply parallelize any C code into parallel code, programmers indeed have to design their code in the proper way.

 

[Exophase]

"Reconfigurable" is more of buzzword to draw attention. It says so because these PEs can work independently, not in a classic SIMD way. It is indeed somehow similar to GPU architectures, having loads of PE running in parallel. Those simple PEs are usually implemented without pipeline, but you can implement pipelines in software(assigning multiplication and addition to different PEs in something like "return a*b+c").
There won't be any compiler to simply parallelize any C code into parallel code, programmers indeed have to design their code in the proper way.

Do you happen to have any information beyond the obvious that Zii has made available? That you maybe know something we don't. Zii has also said that the units are SIMD - if they're all scalar units like you're suggesting then using the term SIMD to describe the parallel computation of the multiple units would be a blatant lie.

I'm not sure you understand what pipelines are exactly when it comes to microprocessor like units. If the PEs are conventional microprocessor like units that aren't pipelined then they're going to be really lousy. Pipelining is transparent to execution and not something you can implement in software per se since it's just a performance optimization (it'd be like implementing an L1 cache in software, it doesn't really make sense). I think you're thinking of superscalar execution per-unit.