1.3.1 MPU Subsystem Description
The Cortex-A15 MPU subsystem integrates the following submodules:
. . ARM Cortex-A15 MPCore
- Two central processing units (CPUs)
- ARM Version 7 ISA: Standard ARM instruction set plus Thumb-®-2, Jazelle-® RCT Java-¢
accelerator, hardware virtualization support, and large physical address extensions (LPAE)
- Neon-¢ SIMD coprocessor and VFPv4 per CPU
- Interrupt controller with up to 160 interrupt requests
- One general-purpose timer and one watchdog timer per CPU
- Debug and trace features
- 32-KiB instruction and 32-KiB data level 1 (L1) caches per CPU
. . Shared 2-MiB level 2 (L2) cache
. . 48-KiB bootable ROM
. . Local power, reset, and clock management (PRCM) module
. . Emulation features
. . Digital phase-locked loop (DPLL)
1.3.2 DSP Subsystem Description
The DSP subsystem contains the following submodules:
. . TMS320DM64-¢ 32-bit fixed DSP core for audio processing and general-purpose imaging and video
processing. It is backward compatible with existing C64x-¢ video codecs.
- 32-KiB L1 4-way set associative cache
- 128-KiB L2 8-way set associative cache
. . Enhanced direct memory access (DMA_DSP) engine with 128 channels for video/audio data transfer
between IVA3 local memories and external SDRAM memories or peripherals
. . Interrupt controller (INTC) with up to 128 interrupt requests
. . Memory management unit (MMU) for address management. It translates virtual addresses handled by
the DSP CPU into physical addresses.
. . DPLL
The DSP subsystem allows direct access to the ABE subsystem, and has emulation capabilities.
1.3.4 Image Processing Unit (IPU) Subsystem
The Cortex-M4 IPU subsystem includes the following components:
. . Two Cortex-M4 CPUs
. . ARMv7E-M and Thumb-2 instruction set architecture
. . Hardware division and single-cycle multiplication acceleration
. . Dedicated INTC with up to 63 physical interrupt events with 16-level priority
. . Two-level memory subsystem hierarchy
- L1
32-KiB shared cache memory
- L2 ROM + RAM
. . 64-KiB RAM
. . 16-KiB bootable ROM
. . Cortex-M4 system bus directly connected to the ISS interconnect
. . MMU for address translation
. . Integrated power management
. . Emulation feature embedded in the Cortex-M4
1.3.7 Imaging Subsystem (ISS)
The ISS processes data coming from the image sensor, memory, and IVA-HD subsystem. The ISS is
responsible for multimedia applications such as: camera viewfinder; video record with up to 1080p at 60fps or stereoscopic record up to 1080p at 30 fps with digital zoom, video stabilization, rotation and auto-convergence. The ISS supports a pixel throughput of up to 304 MP/s. It assures good performance with
sensors up to 24 MP and more (higher resolution can be achieved using vertical frame division mode).
ISS supports still image capture during video record. The ISS can implement third-party algorithms for
further flexibility when working with image sensors.
The ISS consists of:
. . The ISP, which deals with on-the-fly or memory-to-memory data processing. It allows data collection
for autoexposure, autowhite balance, autofocus, resizing, and histogram generation. The ISP consists
of:
- Image pipe interface (IPIPEIF) for synchronization signals (HD, VD) for the ISIF, IPIPE, RSZ, and
hardware 3A (H3A) modules, and data transfer from video port, SDRAM, ISIF. Various pixel data
manipulation functions.
- Image pipe (IPIPE) front-end and back-end modules for raw data processing and RGB and YUV
data processing, respectively. They support:
. . Sensor data linearization for dynamic range extension
. . Programmable 2D lens shading compensation correction
. . Black-level compensation
. . Defect pixel correction (LUT_DPC) with look-up table
. . Defect pixel correction (OTF_DPC) with on-the-fly detection and correction
. . Green imbalance correction (GIC)
. . Gamma correction
. . RGB color correction
. . RGB to YUV4:2:2 color conversion
. . 3D look up table (LUT) for color correction
. . 2D noise filtering
. . 2D edge enhancement
. . False chroma suppression
- H3A for autowhite balance, autoexposure, and autofocus
- Two independent resizers, which allow YUV4:2:2 to YUV4:2:0 planar chroma filtering and
downsampling. The resizers support input and output flows with up to 304 MP/s, and memory-to-
memory rescaling in the range Ã1/4096 scale down, and Ã20 scale up. RGB565, ARGB888,
YUV422 co sited and YUV4:2:0 planar (NV12 or NV21) data output.
- Image sensor interface (ISIF) can process the incoming data and supports the following main
functions:
. . Sensor data linearization
. . Supports VGA read out mode
. . Color space conversion
. . Digital clamp with horizontal/vertical offset drift compensation
. . Vertical line defect correction
. . Programmable 2D-matrix lens shading correction
. . 10-to-8 bits A-Law compression table inside
- Buffer logic (BL), which processes and manages the requests to the module and memory
subsystem
. . Peripheral serial interfaces for connection with sensors and memories:
- One MIPI CSI-2 compliant with four RX data lanes
- One MIPI CSI-2 compliant with two RX data lanes
- One MIPI CSI-2 compliant with one RX data lane / MIPI CSI-1 / CCP2
. . Peripheral 16-bit parallel interface, BT656 and SYNC mode
. . SIMCOP coprocessor for memory-to-memory operation; JPEG encode/decode hardware acceleration;
high-ISO filtering; block-based rotation; warping and fusion; and general-purpose imaging acceleration.
The SIMCOP includes the following main submodules:
- Two imaging extension (iMX) modules - programmable image and video processing engines
- Noise filter 2 (NSF2) - for advanced noise filtering and edge-enhancement
- Noise filter 3 (NSF3) - next generation NSF for advanced noise filtering and edge-enhancement,
supporting Bayer RGB format
- Variable-length coder/decoder for JPEG (VLCDJ) module
- Discrete cosine transform (DCT) module
- Warping accelerator for lens distortion correction (LDC) and chromatic aberration correction
- Rotation accelerator (ROT) engine
- Hardware sequencer, which offloads sequencing tasks from the MPU
- Shared buffers/memories
- DMA controller
. . Timing control module for CAM global reset control, CAM flash strobe, and CAM shutter
. . Bayer scaler module allowing low latency still image capture and stabilization statistics collection.
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