On my A3000 (RISCOS 3.1) it has proper 32 bit addressing and cooperative multitasking. I don't know if this is true of later versions on the RISCPC.
RISC OS 3.1 only supported 26-bit PC mode (though you could use 32 bit addresses to read and write memory, which I guess is where the confusion arises). RISC OS 5 supports 32-bit PC addressing, which enables it to run on the Iyonix from Castle, which uses some XScale chip (and doesn't support the older 26-bit addressing). In the other fork of the OS, RISC OS 4.42 is also 32-bit and runs on the A9 Home - which presumably means RISC OS 6 is similarly 32-bit. It's the RISC OS 5/Iyonix fork that's in the process of being open-sourced, by the way.
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There is some custom hardware so it may be difficult to port.
RISC OS 5 has some form of abstracted HAL, but I don't know how extensive it is.
There has been some discussion of Pandora on the RISC OS newsgroups (see [url="http://groups.google.com/group/comp.sys.acorn.misc/browse_thread/thread/bb05d1246f9d7fe9"this thread on google groups[/url]
The main problem identified is some difference between ARM code in the Cortex A series and all previous ARM chips, but I'm not sure exactly what (pipeline lengths keep getting mentioned, but no-one who knows anything is being very explicit). An unknown (to me) proportion of RISC OS is still hand-written ARM code, so it's not just a matter of tweaking compiler options and hitting 'go'.
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I looked at this before but you need a RISCPC to build it.
That's surprising, given some of the stuff on RiscOSOpen won't even run on an old RISC PC (you need an Iyonix, or possibly an A9 Home). Plus historically, RISC OS itself wasn't built on hardware capable of running RISC OS natively. I guess the riscosopen guys have included some makefiles for use with standard RISC OS build chains, for the benefit of users who don't have access to other hardware.
(Oh, and there's also Pandora spam in some of the Acorn newsgroups by a certain Raj Takhar - grr!)