New Arm Proc, Pandora 2 Anyone?

[Exophase]

A5: 1.5 DMIPS/MHz single-issue
A8: 2.0 DMIPS/MHz in order dual-issue
A9: over 2.0 DMIPS/MHz out of order dual-issue

This coming from a guy who thinks DMIPS are meaningless But I see this is the new Cortex-Ax chip you foreshadowed earlier. The one I speculatively called Cortex-A0.

This is weird though, why would ARM even mention Atom with their less powerful chip? It's just not a competitor. And now the ignorant news sources are following that note and exaggerate it, and this leads to people posting here asking for the new chip to be used in another Pandora.

The chip itself doesn't look very interesting. Looks like an ARM11 with the latest instruction set to me. This "limited dual issue for branches" sound a lot like branch folding which I believe the ARM11 had. Just from the high level details the only big advantage I see is a 1 cycle load-use penalty instead of a 2 cycle one. Is that really enough to bring it from their ARM11 performance figure, which I believe was 1.25 DMIPS/MHz? Their claims from ARM7 to ARM9 weren't that big and that included up to 2 cycles improvement on loads and 1 cycle improvement on stores. Maybe their compiler got better in the mean time.

Also. Where's the L2 cache? No L2 cache is such a big loss that it totally tanks their DMIPS comparisons. We already know from Cortex-A8 with and without L2 enabled that it makes a dramatic difference.

 

[juniorm33]

Sorry, forgot to add methanol fuel-cell power source! <_<

As far as I see it any "new" version is going to be an evolution: case and input control changes, from feedback, to improve on V-1.0 while making manufacturing easier and most likely putting in the fastest available backwards compatible ARM chip.

Plus maybe a new improved screen with the possible inclusion of improved wireless (n-spec, 3G or whatever next-gen pops up) and maybe A-GPS.

knew would make you bite in the end Whooohahahahahaha

 

[Loon]

I'm willing to talk about it though if someone starts another thread, if someone has some experience with having done it. I know from Micromen that it worked well for Acorn then turned around and wrecked them.

That would be an interesting discussion, it would help though if we (the customers) had an official explanation of the current structure of Open Pandora.

My understanding is that it's a partnership, with the partners being Craig, ED & M Weston. This however is based largely on speculation and gut feeling. Just a brief overview or a link to the information would be fine.

If you feel like giving an answer Craig, or anyone else in the know, it might be worth a new thread.

 

[pferguso]

A5: 1.5 DMIPS/MHz single-issue
A8: 2.0 DMIPS/MHz in order dual-issue
A9: over 2.0 DMIPS/MHz out of order dual-issue

This coming from a guy who thinks DMIPS are meaningless But I see this is the new Cortex-Ax chip you foreshadowed earlier. The one I speculatively called Cortex-A0.

This is weird though, why would ARM even mention Atom with their less powerful chip? It's just not a competitor. And now the ignorant news sources are following that note and exaggerate it, and this leads to people posting here asking for the new chip to be used in another Pandora.

The chip itself doesn't look very interesting. Looks like an ARM11 with the latest instruction set to me. This "limited dual issue for branches" sound a lot like branch folding which I believe the ARM11 had. Just from the high level details the only big advantage I see is a 1 cycle load-use penalty instead of a 2 cycle one. Is that really enough to bring it from their ARM11 performance figure, which I believe was 1.25 DMIPS/MHz? Their claims from ARM7 to ARM9 weren't that big and that included up to 2 cycles improvement on loads and 1 cycle improvement on stores. Maybe their compiler got better in the mean time.

Also. Where's the L2 cache? No L2 cache is such a big loss that it totally tanks their DMIPS comparisons. We already know from Cortex-A8 with and without L2 enabled that it makes a dramatic difference.

I salute your nerdiness!

 

[Pleng]

We could speed things up if we sold shares to raise cash, but things like that get messy. Too many cooks and all that.

As long as you own 51% ownership there's no issue of 'too many cooks'. You could also issue non-voting shares so that you are realistically the only one who has the power to make decisions. You could, for example, issue 20,000 shares at, say 1 pound each, divide them up so that you own 10,001, you sell 5999 to raise additional capital (and give 4000 as gifts to the pre-orderers, of course )

If you didn't pay for your own shares you would be liable for their initial value (10,001 pounds) should the company ever fold but that's a lot less risky than as a sole trader - where everything you own is on the line.

Any of your own money that you have put into the venture so far can be capitalized to go towards the 10,001 that you 'owe' the company in share value.

 

[musicalwoods]

A5: 1.5 DMIPS/MHz single-issue
A8: 2.0 DMIPS/MHz in order dual-issue
A9: over 2.0 DMIPS/MHz out of order dual-issue

This coming from a guy who thinks DMIPS are meaningless But I see this is the new Cortex-Ax chip you foreshadowed earlier. The one I speculatively called Cortex-A0.

This is weird though, why would ARM even mention Atom with their less powerful chip? It's just not a competitor. And now the ignorant news sources are following that note and exaggerate it, and this leads to people posting here asking for the new chip to be used in another Pandora.

The chip itself doesn't look very interesting. Looks like an ARM11 with the latest instruction set to me. This "limited dual issue for branches" sound a lot like branch folding which I believe the ARM11 had. Just from the high level details the only big advantage I see is a 1 cycle load-use penalty instead of a 2 cycle one. Is that really enough to bring it from their ARM11 performance figure, which I believe was 1.25 DMIPS/MHz? Their claims from ARM7 to ARM9 weren't that big and that included up to 2 cycles improvement on loads and 1 cycle improvement on stores. Maybe their compiler got better in the mean time.

Also. Where's the L2 cache? No L2 cache is such a big loss that it totally tanks their DMIPS comparisons. We already know from Cortex-A8 with and without L2 enabled that it makes a dramatic difference.

This is the successor to the ARM9/ARM11. It is meant for low-cost products that don't need as much processing power as things with the A9 (think free-on-contract smartphones). It has 80% more DMIPS/mW than ARM9 and 20% more than ARM11 while using 33% less die space than ARM11. It also allows binaries compiled for the Cortex-A class to run without recompilation. I see this being very popular for cheap Android handsets/MIDs.

(Stats shamelessly stolen from multiple comments on Ars Technica and linked ARM presentations)

ARM let its marketing folks get ahold of this announcement and run with it. ARM is promoting it as a good smartbook (ARM laptop) processor when the Cortex-A8/9 will probably dominate that segment (if that segment actually takes off, which I hope it does. I so want a dual-core A9 linux smartbook!).

 

[Exophase]

This is the successor to the ARM9/ARM11. It is meant for low-cost products that don't need as much processing power as things with the A9 (think free-on-contract smartphones). It has 80% more DMIPS/mW than ARM9 and 20% more than ARM11 while using 33% less die space than ARM11. It also allows binaries compiled for the Cortex-A class to run without recompilation. I see this being very popular for cheap Android handsets/MIDs.

Right, I go back to reiterating my skepticism on the 1.5DMIPS/MHz relative figure for ARM11. DMIPS/mW is even less fair if they're comparing Cortex-A5 on the latest process vs ARM11 on the not so latest process. Why else do you think the jump is so much higher between ARM9 and ARM11 - it's not because ARM11 performs so much better per MHz than ARM9. But let me remind you, ARM is selling IP, not chips. If someone licensed ARM11 today they can put it on a modern process, then the numbers might not work out so much the same.

ARMv7a also doesn't bring a whole lot new to the table over ARMv6-T2 which there are already ARM11 cores that support. Just NEON, and since there are going to be Cortex-A9 cores out with no NEON the compatability won't even be across the board for new ARM devices.

This is obviously superior to ARM11MPCore, I'm not debating that, but it looks more like an incremential update to it than anything to get excited about. It's just housekeeping. ARM has got to market their new stuff regardless of how mundane, but comparing it to Atom is just begging for ridicule.

 

[jlepley]

I'm taking a course in economics, and from what I can see, there is no good reason for OpenPandora to "go public". There are an incredible number of legal hurdles to jump in order to incorporate a business. Real corporations have to hire specialists to handle taxes, fees, and other legal issues. That kind of bureaucracy in a business of four people (it is, technically, four people, right?) all in different countries would simply implode. Trust me, any money you would "raise" by incorporating would not make up for all of the time, money, and effort you would spend doing so.

 

[emil10001]

I'm taking a course in economics, and from what I can see, there is no good reason for OpenPandora to "go public". There are an incredible number of legal hurdles to jump in order to incorporate a business. Real corporations have to hire specialists to handle taxes, fees, and other legal issues. That kind of bureaucracy in a business of four people (it is, technically, four people, right?) all in different countries would simply implode. Trust me, any money you would "raise" by incorporating would not make up for all of the time, money, and effort you would spend doing so.

I went to Start-Up Boot Camp last week, and just about every one of the speakers said not to take money if you can avoid it (including the guy from the VC firm). All videos are online, but these two speakers were probably the most interesting. Although, a couple of them did suggest fund-raising as an alternative, not entirely sure of the distinction, probably that they were mostly warning against taking VC money, as opposed to finding other sources of investors.

 

[ari64]

ARMv7a also doesn't bring a whole lot new to the table over ARMv6-T2 which there are already ARM11 cores that support. Just NEON, and since there are going to be Cortex-A9 cores out with no NEON the compatability won't even be across the board for new ARM devices.

The movw/movt is probably the biggest improvement over ARMv6, especially with a small cache.

I agree that it's basically an incremental update of ARM11.

 

[Exophase]

The movw/movt is probably the biggest improvement over ARMv6, especially with a small cache.

I agree that it's basically an incremental update of ARM11.

movt and movw are part of ARMv6-T2.

 

[guilmon999]

just curious but why does it have to be ARM for our processors there are many other companies that make RISC based processors Like PowerPC or the Tegra from intel (stupid intel) i know that ARM has the most market for mobile processors but is there no other company that we can rely on

 

[Exophase]

just curious but why does it have to be ARM for our processors there are many other companies that make RISC based processors Like PowerPC i know that ARM has the most market for mobile processors but is there no other company that we can rely on

Show me a non-ARM mobile solution that beats it on both performance and power consumption. SH CPUs are the only other mobile geared superscalar RISC CPUs I know of (not counting DSPs) and soon Cortex-A9 will be out which will be the only out of order mobile solution I know of, period. Even Atom doesn't provide that.

 

[Tensuke]

just curious but why does it have to be ARM for our processors there are many other companies that make RISC based processors Like PowerPC or the Tegra from intel (stupid intel) i know that ARM has the most market for mobile processors but is there no other company that we can rely on

NVidia makes Tegra...And it uses ARM11 cores.

 

[lulzfish]

tl;dr: Because ARM is the only good one at the moment.

 

[musicalwoods]

just curious but why does it have to be ARM for our processors there are many other companies that make RISC based processors Like PowerPC or the Tegra from intel (stupid intel) i know that ARM has the most market for mobile processors but is there no other company that we can rely on

There are multiple companies that produce ARM SoCs. TI, Qualcomm, Samsung, Freescale, NVIDIA, NEC, Broadcom, ST Microelectronics, Creative, etc. It isn't one company. ARM just makes the IP for the CPU. Imagination Technologies makes the IP the of GPU. TI combines it all with a DSP into their own SoC.

And the Tegra is an ARM11 core with NVIDIA's own GPU. Intel doesn't even touch that one.


Also, basically no RISC processor is better for mobiles at the moment.

EDIT: Wow. Three posts while I was creating this response...

 

[bnolsen]

It is something I've sat in the garden and though about for lengthy periods. It would probably just lead to disaster, the initial funds would be nice, but it might work against us later.

You're not the only one to ask, I've had dozens of emails, possibly over 100 - that is in the last 3 years though.

It's a case of, oh I don't know, it's like why do it when we are moving along (slowly) yet without debt. But then I see the advantage of it. Then the disaster of it.

I go in loops like that. I'm willing to talk about it though if someone starts another thread, if someone has some experience with having done it. I know from Micromen that it worked well for Acorn then turned around and wrecked them.

If the investment came from someone who was hoping to make their money back by selling pandora software/hardware accessories, it could be a win. Investment for the sake of investment can be dangerous since likely the investor's priorities will be quite different.

 

[Sitwon]

Is anyone who is asking about going public planning on investing their own money?

Investors don't just give away their hard-earned cash. They're going to expect returns to make it worth their while. That expectation will bias the design and management decisions in favor of a higher profit margin, not a better product.

 

[Sphinxter]

Let's just wait for the A5.

 

[ldesnogu]

A5: 1.5 DMIPS/MHz single-issue
A8: 2.0 DMIPS/MHz in order dual-issue
A9: over 2.0 DMIPS/MHz out of order dual-issue

This coming from a guy who thinks DMIPS are meaningless But I see this is the new Cortex-Ax chip you foreshadowed earlier. The one I speculatively called Cortex-A0.

Well I have to be careful not to provide data that isn't public And this is what ARM quotes, so...
My aim was just to show that A5 isn't meant for the same level of pure performance as A8 and A9. So using it in a future Pandora would certainly be a wrong decision given that single thread performance would be lower unless the clock is seriously upped, which would cause other issues.

The chip itself doesn't look very interesting. Looks like an ARM11 with the latest instruction set to me. This "limited dual issue for branches" sound a lot like branch folding which I believe the ARM11 had. Just from the high level details the only big advantage I see is a 1 cycle load-use penalty instead of a 2 cycle one. Is that really enough to bring it from their ARM11 performance figure, which I believe was 1.25 DMIPS/MHz? Their claims from ARM7 to ARM9 weren't that big and that included up to 2 cycles improvement on loads and 1 cycle improvement on stores. Maybe their compiler got better in the mean time.

Cortex-A5 is a completely new design, it's no incremental update to ARM11.

BTW going wider issue-wise and reducing L1 load-use penalty aren't the only ways to increase performance; in the particular case of Dhrystone a faster multiplier can make a difference for instance. IMHO improved branch prediction is the key thing.

Of course, A5 was not only designed with Dhrystone in mind

Also. Where's the L2 cache? No L2 cache is such a big loss that it totally tanks their DMIPS comparisons. We already know from Cortex-A8 with and without L2 enabled that it makes a dramatic difference.

Cortex-A9 has no L2 either, it's external: PL310. Note however that some special tuning was done to get a good match between A9 and PL310 (ref).

Oh and you should look closer at Dhrystone: everything fits in L1