Mips And Gflops


1magus

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I know the CPU in the Pandora can be 2000MIPS running @ 1.0GHz, so would it be safe to say the Pandora can do 1200MIPS, -400 MHZ would be -800MIPS?
I'm trying to figure out FLOPS to compare to other devices like PSP, PS2, Dreamcast etc...... but the exactly FLOPS and MIPS is hard to come by in google due to MIPS also being referred to as a CPU in a search engine.
 
Well, no one has safely OCed a pandora to 1 GHz, so no to the 2000. If it's a 1:1 ratio, then the pandora can actually run at 1600 MIPS, since it safely overclocks to 800 MHz (correct me if I'm wrong)
 
Willrandship said:
Well, no one has safely OCed a pandora to 1 GHz, so no to the 2000. If it's a 1:1 ratio, then the pandora can actually run at 1600 MIPS, since it safely overclocks to 800 MHz (correct me if I'm wrong)
Well sure at 800 but I mean at 600.
 
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Doesn't MIPS depend heavily on which instructions you're running?
And the FLOPS will be deceptively low since ARM CPUs don't usually excel at floating-point. I guess you could add in the theoretical maximum of NEON, the DSP (wait that's integer isn't it), and the GPU combined, but:

No matter what you do, none of those figures will have much meaning.
 
lulzfish said:
Doesn't MIPS depend heavily on which instructions you're running?
And the FLOPS will be deceptively low since ARM CPUs don't usually excel at floating-point. I guess you could add in the theoretical maximum of NEON, the DSP (wait that's integer isn't it), and the GPU combined, but:

No matter what you do, none of those figures will have much meaning.
Well than how do you compare the Pandora to other devices that don't run ARM?
 
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"MIPS" stands for "millions of instructions per second." Unfortunately, companies have often said MIPS when they actually mean "DMIPS", or the result of the Dhrystone benchmark normalized against a score obtained on a VAX 11/780, a machine advertised as being capable of executing 1 million instructions per second (but actually typically performed at a much lower rate).

2 instructions per clock cycle is a theoretical maximum on Cortex-A8. In practice you'll rarely achieve anywhere close to this because of stalls that occur due to things like:

- Register dependencies preventing dual pipeline pairing pairing
- Register dependencies stalling operations with multiple cycle latencies like loads and multiplies
- Branch mispredictions
- L1 cache misses and worse, L2 cache misses

ARM has reported a typical throughput of only 0.9 instructions per cycle on their reference A8 implementation (tested over several "industry standard applications"). I would expect OMAP3's would be worse due to poor memory latency.

GFLOPS stands for giga floating point operations per second, and is a function of floating point operations per cycle and clock speed. With NEON, ARM is capable of performing two floating point operations per cycle, or four if you consider a multiply and accumulate instruction to be two operations (advertisements typically do). I say this in spite of NEON's very high MADD latency, which would make it hard to sustain full rate with. PSP, PS2, and Dreamcast, all having computational units designed for gaming, are capable of more FLOPs per clock cycle. The SGX on OMAP3 also has a FLOPs per cycle rate which I expect is 1 MADD per USSE (so two per cycle with SGX530), but it might be two MADDs per USSE instead.
 
Exophase said:
"MIPS" stands for "millions of instructions per second." Unfortunately, companies have often said MIPS when they actually mean "DMIPS", or the result of the Dhrystone benchmark normalized against a score obtained on a VAX 11/780, a machine advertised as being capable of executing 1 million instructions per second (but actually typically performed at a much lower rate).

2 instructions per clock cycle is a theoretical maximum on Cortex-A8. In practice you'll rarely achieve anywhere close to this because of stalls that occur due to things like:

- Register dependencies preventing dual pipeline pairing pairing
- Register dependencies stalling operations with multiple cycle latencies like loads and multiplies
- Branch mispredictions
- L1 cache misses and worse, L2 cache misses

ARM has reported a typical throughput of only 0.9 instructions per cycle on their reference A8 implementation (tested over several "industry standard applications"). I would expect OMAP3's would be worse due to poor memory latency.

GFLOPS stands for giga floating point operations per second, and is a function of floating point operations per cycle and clock speed. With NEON, ARM is capable of performing two floating point operations per cycle, or four if you consider a multiply and accumulate instruction to be two operations (advertisements typically do). I say this in spite of NEON's very high MADD latency, which would make it hard to sustain full rate with. PSP, PS2, and Dreamcast, all having computational units designed for gaming, are capable of more FLOPs per clock cycle. The SGX on OMAP3 also has a FLOPs per cycle rate which I expect is 1 MADD per USSE (so two per cycle with SGX530), but it might be two MADDs per USSE instead.
SO can FLOPS be considered the closest thing to compare computing power with different types of CPUs?
I mean what exactly is NEON and USSE and MADD.
 
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TylerAW said:
lulzfish said:
No matter what you do, none of those figures will have much meaning.
Well than how do you compare the Pandora to other devices that don't run ARM?
You can't, really.
You can only compare specific applications.
I'm not sure what the end would be of such a comparison. Do you want to say, "Extensive testing has found that the Pandora is somewhere between a PS1 and a PS2"? It can't emulate PS2 games, and they won't be ported unless they're open-source homebrew games or something.

Edit:
NEON is the floating-point unit in the OMAP3. It's like a tiny extra CPU that only does floating-point math.
I don't know what USSE is, ask Wikipedia.
I guess from the SSE that it's part of the Streaming SIMD Extensions that some x86 chips have, where they have extra silicon to handle specific vector math. It's similar to NEON, a special chip that does special things that can't really be reduced to a pure "speed" number.
MADD I think is Multiply-then-Add, which some processors can do in one step. However, Exophase says that there is some latency in NEON's MADD implementation, so it might not be exactly 2x as fast, and real applications are not 100% MADD-based anyway.

Again, it's not fair to compare FLOPS since most applications use an unpredictable and complex combination of floating-point math, integer math, memory accesses, GPU transform, GPU lighting, and even I/O access.

Comparing FLOPS between 2 CPUs would be like comparing two pointless things and somebody think of a better analogy.
 
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Exophase said:
"MIPS" stands for "millions of instructions per second." Unfortunately, companies have often said MIPS when they actually mean "DMIPS", or the result of the Dhrystone benchmark normalized against a score obtained on a VAX 11/780, a machine advertised as being capable of executing 1 million instructions per second (but actually typically performed at a much lower rate).

2 instructions per clock cycle is a theoretical maximum on Cortex-A8. In practice you'll rarely achieve anywhere close to this because of stalls that occur due to things like:

- Register dependencies preventing dual pipeline pairing pairing
- Register dependencies stalling operations with multiple cycle latencies like loads and multiplies
- Branch mispredictions
- L1 cache misses and worse, L2 cache misses

ARM has reported a typical throughput of only 0.9 instructions per cycle on their reference A8 implementation (tested over several "industry standard applications"). I would expect OMAP3's would be worse due to poor memory latency.

GFLOPS stands for giga floating point operations per second, and is a function of floating point operations per cycle and clock speed. With NEON, ARM is capable of performing two floating point operations per cycle, or four if you consider a multiply and accumulate instruction to be two operations (advertisements typically do). I say this in spite of NEON's very high MADD latency, which would make it hard to sustain full rate with. PSP, PS2, and Dreamcast, all having computational units designed for gaming, are capable of more FLOPs per clock cycle. The SGX on OMAP3 also has a FLOPs per cycle rate which I expect is 1 MADD per USSE (so two per cycle with SGX530), but it might be two MADDs per USSE instead.

I really do think it's awesome that you don't mind giving us extremely comprehensive answers like this. Unfortunately, I don't understand more than 50% of it (probably a lot less, actually) and I'm a third-year CS major.

I'll try to unpack this a bit, but keep in mind that I've never actually been taught any of this, I've mostly picked it up from reading your posts combined with half-remembered comments from other places, so I could be quite wrong (please correct me if this is the case and you don't mind taking the time):

- "Register dependencies preventing dual pipeline pairing pairing" : a CPU can only execute more than one instruction per cycle if the instructions don't each affect the same registers, so if they do, the instructions can't be scheduled together.
- "Register dependencies stalling operations with multiple cycle latencies like loads and multiplies" - if an operation affecting a particular register or set of registers takes more than one cycle to execute, those registers can't be used for other operations in the meantime.
- "Branch mispredictions" - when filling the pipeline modern CPUs can assess the probabilities of the results of particular instructions, but if they predict the results of a branch incorrectly, the pipeline has to be flushed and refilled from another location.
- "L1 cache misses and worse, L2 cache misses" - CPUs store frequently-accessed data and instructions in cache on the CPU die, which has the advantage of very fast access times, but if it encounters the need to load data that isn't in the cache, it has to load it from main memory, which can take hundreds of cycles.

Am I generally correct here?

lulzfish seems to do a good job explaining the rest. :)
 
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this is what you get if you ask again about comparing different family CPU's.

in simple words, (more easy for people aware of pandora line of events)
you get time stalls when you wait for:
1) I/O operations. (like us waiting for the cases arrive)
2) wrong branch prediction. (took the wrong path so 2 days to get the packets back XD).
3) non parallelize-able actions (cant etch pcb's and populate them at the same time (and cannot be done in different order)).
4) doing something that takes more time than expected ( like the mould factory ).
5) unprepared or missing stuff (like doing MP and running out of boards or cases).
 
I'm going to guess which device is more powerful and you all fill in the blanks :p

Going from highest to lowest, highest being more powerful than the lower ones.
1. PS2 (4MB VRAM is it possible the Dreamcast can do more things than the PS2? :p )
2. Pandora (256 MB RAM)
3. PSP (32MB RAM but 8 is reserved by the OS. 8?! Yeah 8 :p )
4. Dreamcast (Can do higher resolution than PSP with 8MB of VRAM in the PowerVR contain in the Dreamcast, the PSP has 2MB of VRAM)

I know RAM is just one aspect but I took others into account just trying to simplify it. Maybe the Pandora is faster than the PS2 though now that I think about it but just not fast enough to emulate the PS2 so I got confused oh well.
 
TylerAW said:
I'm going to guess which device is more powerful and you all fill in the blanks :p

Going from highest to lowest, highest being more powerful than the lower ones.
1. PS2 (4MB VRAM is it possible the Dreamcast can do more things than the PS2? :p )
2. Pandora (256 MB RAM)
3. PSP (32MB RAM but 8 is reserved by the OS. 8?! Yeah 8 :p )
4. Dreamcast (Can do higher resolution than PSP with 8MB of VRAM in the PowerVR contain in the Dreamcast, the PSP has 2MB of VRAM)

I know RAM is just one aspect but I took others into account just trying to simplify it. Maybe the Pandora is faster than the PS2 though now that I think about it but just not fast enough to emulate the PS2 so I got confused oh well.
im sorry but this is the very first time i've seen ordering processing power with RAM.

this is like counting cars horsepower comparing with the size of the fuel tank
 
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DroneB Dev said:
TylerAW said:
I'm going to guess which device is more powerful and you all fill in the blanks :p

Going from highest to lowest, highest being more powerful than the lower ones.
1. PS2 (4MB VRAM is it possible the Dreamcast can do more things than the PS2? :p )
2. Pandora (256 MB RAM)
3. PSP (32MB RAM but 8 is reserved by the OS. 8?! Yeah 8 :p )
4. Dreamcast (Can do higher resolution than PSP with 8MB of VRAM in the PowerVR contain in the Dreamcast, the PSP has 2MB of VRAM)

I know RAM is just one aspect but I took others into account just trying to simplify it. Maybe the Pandora is faster than the PS2 though now that I think about it but just not fast enough to emulate the PS2 so I got confused oh well.
im sorry but this is the very first time i've seen ordering processing power with RAM.

this is like counting cars horsepower comparing with the size of the fuel tank
Read the whole thing I said RAM is just one aspect I know but I know for a fact the Pandora is faster than the Dreamcast and the PSP.
 
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i did read the whole post!.
but still you just cant do such a compare.

do that with cars and you would end up saying a minicooper with a fueltank as big as possible, would win to a sports car with a 1Lt fuel tank.
 
DroneB Dev said:
i did read the whole post!.
but still you just cant do such a compare.

do that with cars and you would end up saying a minicooper with a fueltank as big as possible, would win to a sports car with a 1Lt fuel tank.
These arent cars they are computers ok.
Can we all atleast agree a Phenom Quad or iCore 7 Quad is faster than Pandora? I mean you all keep saying comparing is impossible but you all know what these machines can and can't do. You have seen a PS2 before and seen the Pandora before.
 
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i am sorry but i have to ask, (did you understand what i am saying?).

i know you didn't talk about cars, but do you understand what an analogy is?

and the response to your last post is.

NO!, Not at all. if you gave it just 1kb of ram i would place my bet on the pandora.

they cant be faster than pandora (by themselves).
another analogy for you.

you cant say a car is faster if it has a bigger engine. (heck why i keep talking about cars if i dont like them at all. maybe because more people understand the minimal parts of a car rather than a computer).
a caterpillar has a huge engine, but it can barely move. and a smart has an engine more smaller, but faster for sure.

EDIT:
my analogy for cars and computers take these asumptions.
CPU<=>Engine
Memory(RAM,HDD,FLASH,etc.)<=>Tank.
 
I know what a analogy is :p
But all of you keep saying comparing is useless so why would an Analogy be any better?
I tried FLOPS and MIPS but I guess you can't use those to compare?
 
XD, funny thing that i say you comparing computers using ram as a fact is useless too.
EDIT:

USING RAM IS EVEN WORSE!.

and if you say my analogy is useless then either you dont understand about cars, or you didnt understand the analogy.
either way im done.

you can teach the blind, you can teach the deaf, but you definitely cant teach the stubborn.
 
On the other hand, memory size, past a certain point, matters much less than speed and latency - IIRC the Pandora suffers a bit in this area (although maybe this is mitigated by the L2 cache, that isn't present, at least, on older ARM platforms).
 
Tom` said:
On the other hand, memory size, past a certain point, matters much less than speed and latency - IIRC the Pandora suffers a bit in this area (although maybe this is mitigated by the L2 cache, that isn't present, at least, on older ARM platforms).
So the Pandora has latency issues, how bad are they?
Is it the cache, ram speeds, design etc...?

PS More RAM in my book means extra performance than less RAM :p.
 
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