Exophase said:
This is compiling to VFP right? Is it using fast mode?
What do you mean by fast mode? -ffast-math?
It's just compiled with hardware floats, i.e. it uses floating point instructions. And I ported it really quickly (one evening's effort), so not everything is optimal, obviously.
What I mean is that it's possible for Cortex-A8 to use run many single precision VFP opcodes on the NEON unit (so they're pipelined and not so slow). But this only happens when specific conditions are met. It might not yet be possible to do so in GCC. I'd be very curious if you could hack the conditions and see if the FPS change, and how much (if it still works).
Just bear in mind, that without this, and for the instructions that are not supported, VFP is pretty slow. It's more there for compatibility sake than to be highly useful.
From Cortex-A8 TRM:
CODE
13.5.4 RunFast mode
RunFast mode is the combination of the following conditions:
• the VFP coprocessor is in flush-to-zero mode
• the VFP coprocessor is in default NaN mode
• all exception enable bits are cleared to 0.
In RunFast mode the VFP coprocessor:
• processes subnormal input operands as zeros
• processes results that are tiny before rounding, that is, between the positive and
negative minimum normal values for the destination precision, as zeros
• processes input NaNs as default NaNs
• returns the default result specified by the IEEE 754 standard for overflow, division
by zero, invalid operation, or inexact operation conditions fully in hardware and
without additional latency.
And...
CODE
16.7.2 VFP instruction execution in the NFP pipeline
The NFP pipeline can execute a subset of the VFPv3 data-processing instructions more
quickly than the VFP coprocessor. The following constraints define which VFP
instructions are executable by the NFP pipeline:
• single-precision data-processing operations only
• RunFast mode must be enabled
• scalar only or non-short vector instructions
If these constraints are met, the following instructions can execute in the NFP pipeline:
• FADDS, FSUBS
• FABSS, FNEGS
• FMULS, FNMULS
• FMACS, FNMACS
• FMSCS, FNMSCS
• FCMPS, FCMPES
• FCMPZS, FCMPEZS
• FUITOS, FSITOS
• FTOUIS, FTOSIS
• FTOUIZS, FTOSIZS
• FSHTOS, FSLTOS
• FUHTOS,FULTOS
• FTOSHS, FTOSLS
• FTOUHS, FTOULS.
VFP instructions that execute in the NFP pipeline have results that are 32-bit
single-precision writes to the upper or lower half of the 64-bit register value. A
restriction that applies to VFP instructions executing in the NFP pipeline is that
instruction results cannot be forwarded early to subsequent instructions.
