slaanesh
Certified Guru
re: above post.
But this begs the question: Why is this happening? Why is the cache.pos and the function location so far apart? *scratches head*
I would have thought that all of the A320's memory would have been in the same 256MB memory chunk.
What's going on here? :-/
Anyone?
More info:
The following four lines are output from my debug:
cache.pos is the current memory location of where the dynamic compiler is generating MIPS code.
ie. at 2b40c044 it's generating a JAL FUNC followed by a delay slot NOP.
The address of func is passed in to this generating function. ie. gen_call_function_raw(421bf4)
Now the value passed in seems to be correct - ie. The function to be executed is "CPU_Intetrupt"
Here's the relevant bit of mipsel-linux-objdump -S of dosbox.dge:
Here's the gdb output:
Noice the PC is 20421bf4.
It's used the JAL instruction (0x0c1086fd) from 0x2b40c044 to jump here, I believe.
However the mystery is that JAL has a 28 bit index and takes the upper 4 bits from the address of the delay slot instruction, which is as 0x2b40c048.
Shouldn't it be jumping to 2b421bf4? This would be the correct spot.
Anyone know what's wrong here? Should I be using JALR instead?
But this begs the question: Why is this happening? Why is the cache.pos and the function location so far apart? *scratches head*
I would have thought that all of the A320's memory would have been in the same 256MB memory chunk.
What's going on here? :-/
Anyone?
More info:
The following four lines are output from my debug:
Code:
cache.pos=2b40c044
jal func [gen_call_function_raw(421bf4)]
cache.pos=2b40c048
nop
cache.pos is the current memory location of where the dynamic compiler is generating MIPS code.
ie. at 2b40c044 it's generating a JAL FUNC followed by a delay slot NOP.
The address of func is passed in to this generating function. ie. gen_call_function_raw(421bf4)
Now the value passed in seems to be correct - ie. The function to be executed is "CPU_Intetrupt"
Here's the relevant bit of mipsel-linux-objdump -S of dosbox.dge:
Code:
00421bf4 <_Z13CPU_Interruptjjj>:
cpu.exception.error=error;
CPU_Interrupt(which,CPU_INT_EXCEPTION | ((which>=8) ? CPU_INT_HAS_ERROR
: 0),reg_eip);
}
Bit8u lastint;
void CPU_Interrupt(Bitu num,Bitu type,Bitu oldeip) {
421bf4: 3c1c006a lui gp,0x6a
...
...
Here's the gdb output:
Code:
anthony:/j/dingoo/dosbox-0.73> /l/local/dosbox/mipsel-a320-linux-gnu-gdb.exe -c
core.146
GNU gdb 6.8
Copyright (C) 2008 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=i686-build_pc-cygwin --target=mipsel-a320-lin
ux-gnu".
Core was generated by `./dosbox.dge'.
Program terminated with signal 11, Segmentation fault.
[New process 146]
[New process 151]
[New process 150]
[New process 149]
#0 0x20421bf4 in ?? ()
(gdb) info registers
zero at v0 v1 a0 a1 a2 a3
R0 00000000 10000400 000010c8 006a0000 00000021 00000001 000010c8 00000000
t0 t1 t2 t3 t4 t5 t6 t7
R8 2ad401e8 00000000 00000001 804abe78 fffffffe 00000001 00000000 00000400
s0 s1 s2 s3 s4 s5 s6 s7
R16 2b009008 000f20c6 00800000 0080200c 006a1938 006a18e0 0063c864 006a1820
t8 t9 k0 k1 gp sp s8 ra
R24 00000008 00000bb7 00000000 00000000 2ad48420 7ff3a820 0080200c 2b40c04c
sr lo hi bad cause pc
00000413 00000000 00000002 20421bf4 00800008 20421bf4
fsr fir
00000000 00000000
(gdb) disassemble 0x20421bf4
No function contains specified address.
(gdb) x 0x2b40c044
0x2b40c044: 0x0c1086fd
(gdb) x 0x2b40c048
0x2b40c048: 0x00000000
(gdb)
Noice the PC is 20421bf4.
It's used the JAL instruction (0x0c1086fd) from 0x2b40c044 to jump here, I believe.
However the mystery is that JAL has a 28 bit index and takes the upper 4 bits from the address of the delay slot instruction, which is as 0x2b40c048.
Shouldn't it be jumping to 2b421bf4? This would be the correct spot.
Anyone know what's wrong here? Should I be using JALR instead?