Cortex-A8 Assembly Timing Analyzer

[Exophase]

I found this posted on the ARM forums:

http://translate.google.com/translate?js=n&prev=_t&hl=en&ie=UTF-8&layout=2&eotf=1&sl=fr&tl=en&u=http%3A%2F%2Fpulsar.webshaker.net%2Fccc%2F

The page is in French, but I've given a google translate link for it in English. The analysis result comments are in English anyway.

Enter in a snippet of ARMv7a code and it will give an outline of what's executed at what cycle, and why stalls occur if present. I can't say exactly how accurate it is, but I know the author has done a lot of timing tests on his Beagleboard. Unfortunately the source isn't available (as far as I can tell), but there's a comment form if you have any corrections.

I've found that this tool is using the mnemonics in the Cortex-A8 TRM rather than the ARMv7a spec. Some of the names are different, and most likely the accepted ones are obsolete. Also, it uses GAS syntax, include ":" for specifying alignment in NEON load/store and not "@."

I've also found at least one instruction that appears to not be recognized, "vsr".. I've reported this to the author, but if you need to use it vsl should have the same timing.

 

[notaz]

Interesting project. Doesn't like most of the NEON code I feed it though, also pseudo-instructions..

 

[Exophase]

I haven't had problems with any NEON so far, what have you tried?

 

[notaz]

some random things from my NEON GTE code:

    vpadd.s32   d16, d16, d17
    vpadal.s32  q2, q8
    vpadal.s32  q3, q9
    vst1.32     d8, [r3]!
    vst1.32     d9[0], [r3]
    vldmia      r3, {q7}
    vshr.s32    d16, d12, #1
    vmin.u32    d11, d28
    vst1.32     d18, [r3]!
    vst1.32     d19[0], [r3]

 

[Exophase]

It needs the following fixes:
- TRM style mnemonics instead of official ones. That means vpadd becomes vsum and vpadal becomes vsma.
- vst has to take register lists.
- You can't use implied destination like you are with vmin (has to be vmin.u32 d11, d11, d28)
- I couldn't get the single-lane store to be detected.. the multiple-lane version have the same timing I think
- I couldn't get vldmia to be detected, but I was wondering why you're using it over vld1
- vshr doesn't work for some reason (I've reported it) but vsl has the same timing.

You should report the other two bugs. Especially if you happen to know French.

 

[Farox]

Very interesting discover from the same author just published about the NEON asm...

http://pulsar.webshaker.net/2011/03/16/optimiser-les-operations-flottantes/
use Google translate for non french users !!
Here the time finally obtained

• gcc without optimization: 32000 cycles
• gcc Optimizing with gcc-O9: 13100 cycles
• Version assembler FFT: 9600 cycles
• NEON assembler version Direct: 2900 cycles

It's pretty good. It is already 4.5 times faster than optimized C version.

 

[DavidBowman]

You guys are just brilliant when it comes to this stuff, and I love it.