The alternative is to use a full address space array, but for 1KB pages in a 4GB space you'd need at least 16MB, which might not mean the design goals of nullDCe.
You can use a two-level approach to reduce memory requirements. But I agree MMU simulation is costly.
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And actually, loads and stores happen all the time - on GBA (ARM + Thumb, with ARM execution being about 40% of the instructions on average) loads/stores can represent over 30% of execution time.
Didn't you mean 30% of instructions? At least that's my experience...
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All in all, if the memory map is simple enough and most reads/writes are going to one region of RAM then it'd be fastest just to check if things fall in there, faster than emulating TLB which can be completely arbitrary.
I'm wondering how much "cleverness" one can put in the MMU/TLB simulation to overcome performance issues. I mean one could write a fully compliant MMU simulation which could optimize things depending on the current mapping. That could work well for "easy mappings", but of course for an OS that does many context switching that wouldn't work that well.
Anyway getting good performance with MMU simulation is a extremely difficult