Dingoo Jzrisc - Mips32R2 Compatible ?

[hlidegp2x]

JzRISC implements MIPS32 Release 2 instruction set architecture; in micro-architecture level, JzRISC deploys a new 8 stage pipelining structure; in user level, it is basically follow MIPS 4KE core user programming interface with some kinds of adjustment. This document summarizes zRISC's difference/adjustment from MIPS 4KE core . MIPS document No. MD00103, "MIPS32™ 4KE™ Processor Cores Software User's Manual" is a supplement to this document.

Features :
JzRISC CPU
• MIPS32 ISA Release I and II.

       Instruction                                  Cycles     Description
       | WAIT                                       | -        | will be repeatedly executed until an  interrupt arise
       | MTC0, CACHE(I), TLBWI/R,  EXT/INS          | 4        | 3 extra interlock cycles
       | ROTR/ROTRV                                 | 3        | 2 extra interlock cycles
       | CACHE(D),  SEB/SEH                         | 2        | 1 extra interlock cycles
       | JALR/BCC                                   | 4/1      | Zero penalty when BTB predict correctly and the branch is taken, otherwise, 3 cycles penalty
       | BCCL                                       | 5/4/2/1  | Zero penalty when BTB taken and real taken, otherwise:
       |                                            |          | 1. BTB miss, branch is taken, 3 penalties
       |                                            |          | 2. BTB miss, branch is untaken, 1 penalty
       |                                            |          | 3. BTB predict taken, branch is untaken, 4 cycles penalty
       |                                            |          | 4. BTB predict untaken, branch is taken, 3 cycles penalty
       | MUL,  MULT/MULTU,  MADD/MADDU,  MSUB/MSUBU | 2/1      | No extra interlock cycle for 32x16 case, 1 extra interlock cycle for 32x32 case
       | DIV/DIVU                                   | 2~34     | Determined by characteristic of divider
       | Others                                     | 1        |

Normally, MIPS32 R1 has CLZ, CLO, MADD, MADDU, MSUB, MSUBU and MUL(result into GPR instead of HI:LO) and MIPS32 R2 has INS/EXT, ROTR/ROTRV, SEB/SEH, WSBH, SYNCI

• 32 32-bit general purpose registers, no shadow GPR
• 8-stage pipeline
• Interlocked implementation
• Virtual address space: 4 G-Bytes

Multiply-Divide Unit (MDU)
• Maximum issue rate of one 32x16 multiply every clock
• Maximum issue rate of one 32x32 multiply every other clock
• Minimum 2 clock cycle, maximum 34 clock cycles for divide

Memory Manager Unit (MMU)
• 4 G-Bytes of address space
• 32/16 dual-entry full associative joint TLB plus 4 dual-entry ITLB
and 4 dual-entry DTLB respectively
• 7 different page size from 4Kb to 16MB supported in any entry
• Support entry lock
• Space identifier ASID: 8 bits
• Small (1K) page not implemented

Data Cache
• Virtually-indexed, physically-tagged
• 4 way, 8-word line, alterable size: 4K, 8K, 16K bytes
• LRU replacement algorithm
• Write-back, write-through
• 16-word depth write buffer
• Cache line lock not implemented

Instruction Cache
• Physically-indexed, physically-tagged
• 4 way, 8-word line, alterable size: 4K, 8K, 16K bytes
• LRU replacement algorithm
• Cache line lock not implemented

Debug&JTAG
• JTAG interface to host machine
• ACC mode to accelerate JTAG memory access
• Two instruction and one data breakpoint

Internal Timer (COP0 Count/Compare)
• N/A

Branch Target Buffer (BTB)
• Virtally-tagged
• Up to 64 entry direct mapped
• 2-bit branch history maintained

Bus Interface
• compliance with AHB protocol

 

[slaanesh]

Very interesting. I will recompile using -mips32 -mtune=mips32r2.

 

[SpearOfAnubis]

Using -mtune=mip32r2 will just panic your OS if it does not emulate them. Jz47xx series implement none of releaseII instructions at all. Alide, I just have some jzsimd stuffs maybe you instrested including complete C representations of jzsimd, its the key file of mips gdb - mips.igen, I just merge all jzsimd instructions in it. I'm a newbie and have no idea of how to share it, email you or other uploading ways?

 

[hlidegp2x]

Using -mtune=mip32r2 will just panic your OS if it does not emulate them. Jz47xx series implement none of releaseII instructions at all. Alide, I just have some jzsimd stuffs maybe you instrested including complete C representations of jzsimd, its the key file of mips gdb - mips.igen, I just merge all jzsimd instructions in it. I'm a newbie and have no idea of how to share it, email you or other uploading ways?

what a pity ! so you're confirming MIPS32R2 are not implemented ? because the cycles of thoses instructions were given by their documentations. And yes I may be interested. I'll PM you.

 

[hlidegp2x]

Using -mtune=mip32r2 will just panic your OS if it does not emulate them. Jz47xx series implement none of releaseII instructions at all. Alide, I just have some jzsimd stuffs maybe you instrested including complete C representations of jzsimd, its the key file of mips gdb - mips.igen, I just merge all jzsimd instructions in it. I'm a newbie and have no idea of how to share it, email you or other uploading ways?

Something is extremely wrong. From 02_cpu_spec.pdf, I can read :

JzRISC core is a high performance and low power implementation of RISC processor. In architecture
level, JzRISC implements MIPS32 Release 2 instruction set architecture; in micro-architecture level,
JzRISC deploys a new 8 stage pipelining structure; in user level, it is basically follow[ing] MIPS 4KE core
user programming interface with some kinds of adjustment. This document summarizes JzRISC’s
difference/adjustment from MIPS 4KE core (marked with red color). MIPS document No. MD00103,
“MIPS32™ 4KE™ Processor Cores Software User’s Manual” is a supplement to this document.

And I can see a table listing some MIPS32r2 instructions :

• ROTR/ROTRV: 3 cycles instead of 1 cycle (2 extra interlock cycles)
• EXT/INS: 4 cycles instead of 1 cycle (3 extra interlock cycles)
• SEB/SEH: 2 cycles instead of 1 cycle (1 extra interlock cycle)

In Allegrex (the MIPS processor of PSP), those instructions are mapped in a different opcode, so one cannot the mips_emit functions from PSP version of gpSP for those instructions.

I wonder if using -mtune=mip32r2 generates an elf file that OS (which one by the way ?) doesn't run because of ELF signature ? or does it let the executable run until a reserved instruction fault is raised ?

I guess I need to reinstall the sdk to check it :/.

 

[SpearOfAnubis]

I believe that runtime can expose truth if you create a experiment program and run it on a320.

 

[hlidegp2x]

I believe that runtime can expose truth if you create a experiment program and run it on a320.

I'm trying it but i cannot find a working program which builds fine :/. I tried guide-how-to-compile-apps-for-dingoo-native-os-without-the-sdk.

 

[hlidegp2x]

I believe that runtime can expose truth if you create a experiment program and run it on a320.

Keeping -mips32 for the binary, SEB and SEH perfectly work on Flatmush's MineSweeper. But to make them work, I was forced to do so :

inline __attribute__((always_inline)) int
 __seb(int x) { int result; __asm__ __volatile__ (".set push; .set noreorder; .set mips32r2; SEB %0, %1; .set pop" : "=r"(result) : "r"(x) : "memory"); return result; }
 inline __attribute__((always_inline)) int
 __seh(int x) { int result; __asm__ __volatile__ (".set push; .set noreorder; .set mips32r2; SEH %0, %1; .set pop" : "=r"(result) : "r"(x) : "memory"); return result; }

I added "if ((__seb(0xFF) != 0xFFFFFFFF) || (__seh(0xFFFF) != 0xFFFFFFFF)) return;" in the game loop, and I was able to run the game so SEB and SEH work. I also checked those lines were present in the elf code with those SEB and SEH instructions :

  80a03b84:    240200ff     li    v0,255
  80a03b88:    7c021c20     0x7c021c20 <--- SEB v1, v0
  80a03b8c:    2402ffff     li    v0,-1
  80a03b90:    14620074     bne    v1,v0,80a03d64 <gameDialog+0x2d8>
  80a03b94:    3402ffff     li    v0,0xffff
  80a03b98:    7c021620     0x7c021620 <-- SEH v1, v0
  80a03b9c:    14430071     bne    v0,v1,80a03d64 <gameDialog+0x2d8>
  80a03ba0:    2405007f     li    a1,127

EDIT: indeed, SEB and SEH don't work, they weren't put at the right place when I tested them.

 

[hlidegp2x]

Ok, I have a very bad news. I was testing in the wrong game loop. Putting the test in the right place freezes the game. So the manual seems a complete lie about MIPS32R2 implementation. Two possibilities : no MIPS32r2 implemenation or they are implemented with no standard opcode (like Allegrex - PSP cpu). Quite disappointin.

EDIT: or Dingoo uses a mips32r2-less variant of JZ4740.

 

[slaanesh]

Maybe a bit late but:


Toolchain:
- GCC updated to 4.6.3, with LTO support
- Optimizes for the jz4740 processor (defaults to mips32 processor, tune to mips32r2)