Features :JzRISC implements MIPS32 Release 2 instruction set architecture; in micro-architecture level, JzRISC deploys a new 8 stage pipelining structure; in user level, it is basically follow MIPS 4KE core user programming interface with some kinds of adjustment. This document summarizes zRISC's difference/adjustment from MIPS 4KE core . MIPS document No. MD00103, "MIPS32 4KE Processor Cores Software User's Manual" is a supplement to this document.
JzRISC CPU
 MIPS32 ISA Release I and II.
		Code:
	
	       Instruction                                  Cycles     Description
       | WAIT                                       | -        | will be repeatedly executed until an  interrupt arise
       | MTC0, CACHE(I), TLBWI/R,  EXT/INS          | 4        | 3 extra interlock cycles
       | ROTR/ROTRV                                 | 3        | 2 extra interlock cycles
       | CACHE(D),  SEB/SEH                         | 2        | 1 extra interlock cycles
       | JALR/BCC                                   | 4/1      | Zero penalty when BTB predict correctly and the branch is taken, otherwise, 3 cycles penalty
       | BCCL                                       | 5/4/2/1  | Zero penalty when BTB taken and real taken, otherwise:
       |                                            |          | 1. BTB miss, branch is taken, 3 penalties
       |                                            |          | 2. BTB miss, branch is untaken, 1 penalty
       |                                            |          | 3. BTB predict taken, branch is untaken, 4 cycles penalty
       |                                            |          | 4. BTB predict untaken, branch is taken, 3 cycles penalty
       | MUL,  MULT/MULTU,  MADD/MADDU,  MSUB/MSUBU | 2/1      | No extra interlock cycle for 32x16 case, 1 extra interlock cycle for 32x32 case
       | DIV/DIVU                                   | 2~34     | Determined by characteristic of divider
       | Others                                     | 1        |Normally, MIPS32 R1 has CLZ, CLO, MADD, MADDU, MSUB, MSUBU and MUL(result into GPR instead of HI:LO) and MIPS32 R2 has INS/EXT, ROTR/ROTRV, SEB/SEH, WSBH, SYNCI
 32 32-bit general purpose registers, no shadow GPR
 8-stage pipeline
 Interlocked implementation
 Virtual address space: 4 G-Bytes
Multiply-Divide Unit (MDU)
 Maximum issue rate of one 32x16 multiply every clock
 Maximum issue rate of one 32x32 multiply every other clock
 Minimum 2 clock cycle, maximum 34 clock cycles for divide
Memory Manager Unit (MMU)
 4 G-Bytes of address space
 32/16 dual-entry full associative joint TLB plus 4 dual-entry ITLB
and 4 dual-entry DTLB respectively
 7 different page size from 4Kb to 16MB supported in any entry
 Support entry lock
 Space identifier ASID: 8 bits
 Small (1K) page not implemented
Data Cache
 Virtually-indexed, physically-tagged
 4 way, 8-word line, alterable size: 4K, 8K, 16K bytes
 LRU replacement algorithm
 Write-back, write-through
 16-word depth write buffer
 Cache line lock not implemented
Instruction Cache
 Physically-indexed, physically-tagged
 4 way, 8-word line, alterable size: 4K, 8K, 16K bytes
 LRU replacement algorithm
 Cache line lock not implemented
Debug&JTAG
 JTAG interface to host machine
 ACC mode to accelerate JTAG memory access
 Two instruction and one data breakpoint
Internal Timer (COP0 Count/Compare)
 N/A
Branch Target Buffer (BTB)
 Virtally-tagged
 Up to 64 entry direct mapped
 2-bit branch history maintained
Bus Interface
 compliance with AHB protocol
 
	
 
 
		 
 
		 
 
		