hlide said:
andys said:
Predicate execution is dependant upon the ARM bits from my reading, and predicated instructions are squashed before they hit NEON. Of course, not a CPU designer, so I may have understood wrong. The NEON bit has arbitary permute and comparison functions, so you can simulate predication on NEON by using VTBX though. I think
Not tried it - don't have an beagleboard, but it looks plausible
If I remember well you cannot issue in the same cycle two instructions having predicates so they must be used with attention.
@andys: VTBX "uses byte indexes in a control vector to look up byte values in a table and generate a new vector. Indexes out of range leave the destination element unchanged". I'm not sure to understand what you want to do here.
Well, I'm not an assembly programmer, so you might want to check that I am sane.
So, my idea is that VTBX takes an array looking something like
[0,1,2,3,4,5,6,7] and then will select the 0th byte, etc upwards of the target. (Obviously for a q register it would go up to 15).
So if you wanted to do an ADD on the first and third elements of a 64bit vector containing 16 bit elements, you could fill it with
[0,1,-1,-1,4,5,-1,-1].
Perform the ADD on the full vector, then use VTBX to select out the first and third of the changed set - thus leaving 2 and 4 unchanged and copying 1 and 3. I assume this is how it works, it's not exactly the best documented instruction ever.
If this is the case, and I'm not insane, then you can do predication by using the compare instructions - the compare instructions leave a 1 in the areas where it matches, and a 0 where it doesn't match. If you do an inverted comparison (if you want all the ones that are greater than a number, you do less than or equal to), and then subtract 1 from all lanes, you would end up with 0 where you want the value and -1 where you don't want the value. If you then or that against the mask [0,1,2,3,4,5,6,7] - you would wind up with the lanes you don't want switched off.
I might be completely barking up the wrong tree, but it seems like this might work. Of course, it's not as cheap as dedicated predication because VTBX takes 2 cycles on a D register, and you'd need to issue two of them for a Q register, as well as a compare, a subtract and an OR, thus costing you at least 4 cycles assuming you were actually able to interleave them, but it strikes me that it would be a lot cheaper than a 20 cycle + stall.
Anyway, am happy to be proved wrong - I don't have hardware to try it with!
For anybody who hasn't read the docs:
VTBX : http://infocenter.arm.com/help/topic/com.arm.doc.dui0204i/CIHCFEBA.html#id6764875
VCGE (and friends) : http://infocenter.arm.com/help/topic/com.arm.doc.dui0204i/CIHGAGID.html
PS: After reading the second one - I don't think you need a subtract, it seems to imply it sets the lane to -1 - which would save you a register and an op, although the VTBX would still dominate, depending upon the other instructions you had to execute. Also, does anybody know HOW the dual issue works - can it back to back dual issue multi-cycle instructions? For example, could it execute VTBX and Qword floating point ops simultaneously, just interleaved? Or does it only work with single cycle ops?