GP32 MHz Table
- Thread starter chui
- Start date
Either download pllset tool from Samsung site or download sources for slightly simplified pllset tool from here: http://www.cs.Helsinki.FI/u/jikorhon/conde...2/dl/pllset.zip and compile that with your favourite C-compiler. Then you can calculate all needed parameters yourself <_<
Robster
Dodgy hardware mod maker
Just to make that a little bit clearer, download the pllset.zip from mr spiv's site, and compile pllset.c for your platform. Then run PLLSET with (say)
PLLSET 132000000
And you'll get a table of output that includes several options for div_factor and clk_mode. You have to choose a div_factor according to the "Selection Guide", one of the conditions is that P==1. To make that easier, I changed line 69 of plllset.c from
if (bm!=256L)
to
if ((bm!=256L) && (pass))
so it only prints out lines where P==1.
So for the example above I get
+---------------------------------------+
| PLL VALUE CALCULATER Ver 1.21+ |
| Fixed for S3C2400X/S3C2410X/S3CA400X |
+---------------------------------------+
Input XTAL0 Freq:12000000
Output MCLK Freq:132000000
M ,P ,S |MCLK |fvco|fi/P+2|PAR1<PAR2<PAR3|P|PAR4|
24h, 0h,1h |132000000|264M| 6.0M| 0.2| 0.4| 0.6|1| 1.0|
3ah, 1h,1h |132000000|264M| 4.0M| 0.2| 0.3| 0.4|1| 0.8|
Selection Guide: choose the nearst one to this guide
1) large SDIV value
2) P == 1
3) 0.7 < PAR4 < 1.8
4) fvcp < 330M
Now, in your call to GpClockSpeedChange you have 3 parameters.
First one is the clock speed (eg 132000000).
Second is clk_div which is a combination of "M,P,S" from the table that PLLSET prints out. It's 5 hex digits, the first 2 are "M", the second 2 are "P", and the last one is "S" so from the table above, clk_div could be 0x24001 or 0x3a011.
The third parameter is clk_mode, and it relates to the MCLK:HCLK
CLK divider. I just use 1 (for HCLK=MCLK/2, PCLK=HCLK) for clock speeds below 75MHz and 2 (for HCLK=MCLK/2, PCLK=HCLK/2) for clock speeds below 150MHz). And I don't go above 150MHz
So, to wrap it all up, the clock speed change example is
GpClockSpeedChange (132000000, 0x24001, 2).
Whew! Does that make sense?
PLLSET 132000000
And you'll get a table of output that includes several options for div_factor and clk_mode. You have to choose a div_factor according to the "Selection Guide", one of the conditions is that P==1. To make that easier, I changed line 69 of plllset.c from
if (bm!=256L)
to
if ((bm!=256L) && (pass))
so it only prints out lines where P==1.
So for the example above I get
+---------------------------------------+
| PLL VALUE CALCULATER Ver 1.21+ |
| Fixed for S3C2400X/S3C2410X/S3CA400X |
+---------------------------------------+
Input XTAL0 Freq:12000000
Output MCLK Freq:132000000
M ,P ,S |MCLK |fvco|fi/P+2|PAR1<PAR2<PAR3|P|PAR4|
24h, 0h,1h |132000000|264M| 6.0M| 0.2| 0.4| 0.6|1| 1.0|
3ah, 1h,1h |132000000|264M| 4.0M| 0.2| 0.3| 0.4|1| 0.8|
Selection Guide: choose the nearst one to this guide
1) large SDIV value
2) P == 1
3) 0.7 < PAR4 < 1.8
4) fvcp < 330M
Now, in your call to GpClockSpeedChange you have 3 parameters.
First one is the clock speed (eg 132000000).
Second is clk_div which is a combination of "M,P,S" from the table that PLLSET prints out. It's 5 hex digits, the first 2 are "M", the second 2 are "P", and the last one is "S" so from the table above, clk_div could be 0x24001 or 0x3a011.
The third parameter is clk_mode, and it relates to the MCLK:HCLK
CLK divider. I just use 1 (for HCLK=MCLK/2, PCLK=HCLK) for clock speeds below 75MHz and 2 (for HCLK=MCLK/2, PCLK=HCLK/2) for clock speeds below 150MHz). And I don't go above 150MHz So, to wrap it all up, the clock speed change example is
GpClockSpeedChange (132000000, 0x24001, 2).
Whew! Does that make sense?
Robster
Dodgy hardware mod maker
I'm sorry, I lied about clk_mode
Just checked my facts.
MCLK is the main clock for the CPU
HCLK is the clock for the system bus (SDRAM, LCD etc)
PCLK is the clock for the peripherals (UARTs, SMC, IIS, timers etc).
The values for clk_mode are:
0 HCLK = MCLK, PCLK = MCLK
1 HCLK = MCLK, PCLK = MCLK / 2
2 HCLK = MCLK / 2, PCLK = MCLK / 2
3 HCLK = MCLK / 2, PCLK = MCLK / 4
So you can only use mode 1 up to about 75MHz because above that the RAM stops working.
Chui: keep up the great work with SDL!
Just checked my facts.
MCLK is the main clock for the CPU
HCLK is the clock for the system bus (SDRAM, LCD etc)
PCLK is the clock for the peripherals (UARTs, SMC, IIS, timers etc).
The values for clk_mode are:
0 HCLK = MCLK, PCLK = MCLK
1 HCLK = MCLK, PCLK = MCLK / 2
2 HCLK = MCLK / 2, PCLK = MCLK / 2
3 HCLK = MCLK / 2, PCLK = MCLK / 4
So you can only use mode 1 up to about 75MHz because above that the RAM stops working.
Chui: keep up the great work with SDL!
ZardozJones
Certified Guru
- Joined
- Jan 28, 2003
- Messages
- 59
80mhz ram 0 is a very good setting - this seems ultra stable and fast!!
There is also this topic with an example from ThunderZ
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Anything above 66MHz for HCLK & PCLK is risky (it is said in Samsung docs).. My GP32 HCLK & PCLK clock nicely over 80MHz but my GP32 is from the first batch of machines, which are somewhat resilient to overclocking etc. My friends GP32 won't allow overclocking HCLK & PCLK speeds above 66MHz even by few kHz without side effects :blink:Robster posted on Aug 20 2003 said:
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