M-HT
Very Active Member
I'm sorry, but I don't understand what you are asking.
add r0, r0, #1
andS r0, r0, #3
beq do_something
Cortex A8 has a pipeline depth of 13 - I'm really lacking on the assembly part, but with that depth I'd hardly expect any guaranteed 1-tick instructions.Well one benefit of ARM over other competing architectures is that in most circumstances you can just count instructions to compare them, since everything other than STM/LDM (and probably a few newer instructions I'm less aware of) takes one tick (apart from branches which you can assume take 5 or so ticks, or whatever your pipeline length is, which is why when you've got an inline conditional where the resulting code is a 4 or less instructions, it's better usually to block it out using a conditional extension like NE or CS - but if you need to loop you're going to have to branch anyway.
Well one benefit of ARM over other competing architectures is that in most circumstances you can just count instructions to compare them, since everything other than STM/LDM (and probably a few newer instructions I'm less aware of) takes one tick (apart from branches which you can assume take 5 or so ticks, or whatever your pipeline length is, which is why when you've got an inline conditional where the resulting code is a 4 or less instructions, it's better usually to block it out using a conditional extension like NE or CS - but if you need to loop you're going to have to branch anyway.
The first parameter goes into register r0, the second into register r1, the third into register r2.I saw these C parameters, but I have no idea how to pass them, and what are their limits.
You see that from a code in the kernel ?
I was about to compile as C and see how it goes with gdb.
You mean for each system call ?