Svartalf
Active Member
http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/
According to this article, here's some ugly sharp edges with NEON use. While it's pipelined, it's async in nature from the A8 itself, meaning there's some memory access hazard prevention silicon in place in the SoC. The CPU and NEON trip all over each other if the NEON's access spans a 16-byte boundary. Timings get pretty evil when this happens (Anywhere from the "nice" 22 cycles to the truly evil 52 cycles to complete an ARM store to RAM immediately in the same domain as a NEON store operation.
Just thought everyone ought to know that one...
According to this article, here's some ugly sharp edges with NEON use. While it's pipelined, it's async in nature from the A8 itself, meaning there's some memory access hazard prevention silicon in place in the SoC. The CPU and NEON trip all over each other if the NEON's access spans a 16-byte boundary. Timings get pretty evil when this happens (Anywhere from the "nice" 22 cycles to the truly evil 52 cycles to complete an ARM store to RAM immediately in the same domain as a NEON store operation.
Just thought everyone ought to know that one...