Mmm.... Something isn't right with that math or every spec I've seen on both the eMMC and the SD protocol are wrong. To my understanding, the eMMC bus speed (theoretical maximum) is 208 MB/s and the uSD and SD bus speed (theoretical maximum) is 104MB/s. Could you have used the -old- MMC and SD specs?
The Pandora got real world reads of just short of 20MB/s on it's SD ports. The Pyra's SoC specs call for SD bandwidth of 2.5x the Pandora's and eMMC bandwidth of twice the SD. Without the switching I'm expecting the eMMC to run around 100MB/s and the uSD card to cap around 50MB/s real world speeds. If you're copying data from one to the other (worst case scenario), Read, switch, write, validate write, switch, repeat... Each bus will be cut roughly in half and some speed will be then lost to the switching overhead.
Worst case scenario, when copying data from one to the other, that switching overhead would be half or less - that is where the 1/4 comes in. So - in that worst case scenario with worst case switching overhead taken into account, I expect the eMMC to be effectively reading at roughly 25 MB/s while writing to the uSD at 12.5 MB/s. Frankly, it should be considerably faster than that as I don't expect the switching overhead to fully half the performance.
Generally, I doubt anyone is going to be spending a lot of time copying files from the eMMC to the uSD. In cases where someone has both present, I would expect a scenario where they boot the OS from the eMMC and have /home on the eMMC.
I'm looking forward to ED being able to run some tests & benchmarks on the final boards with the 32GB eMMC and a solid uSD. I think they'll outperform my above 'worst case scenario'..