GP32 Gp32 Iismod And Iiscon Registers

[slaanesh]

I've been trying to finesse some sound output on the GP32. I've got a pretty good understanding of the lower level working of DMA pushing sound to the IIS. I've got the Samsung documentation um_s3c2400x PDF. Very useful stuff.
However it's a bit unclear with some things and I'd love some bits of this cleared up by someone in the know.

My questions are with IISMOD

1). What is the significance of "master clock frequency select", bit [2]? Allowable values are 0 = 256fs and 1 = 384fs

2). What is the significance of "serial bit clock frequency select", bit [1:0]? Allowable values are 00 = 16fs, 01 = 32 fs, 10 = 48fs and 11 = N/A.

"Master clock frequency select" has some correlation to the sample rate, the xroar 20b source code has a good example of setting this based on calculated sample rate. I'm doing the same thing in my code but I'm just wondering what the significance of both these items are?

 

[slaanesh]

Just another note - I am using 16-bit mode so the only options for "serial bit clock frequency select" are 32fs and 48fs.

CODECLK can be set to either 256fs or 384fs - what does this mean?

If I set CODECLK=384fs, then I can set IISCLK to 48fs (or 32fs). Is there any benefit to setting 48fs? And what does this mean?

Information can be found in um_s3c2400x_rev10.pdf (Google search to find hits), however I need an English explanation.

Thanks for any help.