Floating Point Optimization Tutorial

[Adventus]

Hiya,

I wrote a short tutorial on how to get the best float point performance from the ARM Cortex A8:

http://www.pandorawiki.org/Floating_Point_Optimization

It's targetting GCC (I used CodeSourcery 2007q3) and i tried to make it understandable to most C programmers. I'll probably add to it as i improve my understanding.

Tell me if anything is wrong!

 

[ldesnogu]

Thanks for doing this, that'll be useful for many developers

A few comments:

• the VFP is Lite not due to die area, but because it was decided it was not that useful to have a fully pipelined FPU along NEON; an FPU is not that big especially compared to an SIMD unit such as NEON
• runfast mode is not that fast
• for single precision constants, one can also use the 'f' suffix as in '2.123f'; another thing to check is the use of double precision libm functions; gcc libm has a full array of single precision equivalents
• you should put somewhere the flags to use for vfp and/or neon (-mfpu=neon/vfp mfloat-abi=softfp).
• hopefully one might soon use hardfp instead of sotffp for parameters which will be passed in fpu registers

 

[Adventus]

Thanks for the comments, very useful information. Will add it soon.

runfast mode is not that fast

Can you give an indication of exactly how fast? In the technical reference it doesn't give instruction timings but simply states they execute in the NEON pipeline.... i assumed that means 1 FMAC per cycle....

BTW congratulations on the getting a Beagleboard from the contest.

 

[ldesnogu]

runfast mode is not that fast

Can you give an indication of exactly how fast? In the technical reference it doesn't give instruction timings but simply states they execute in the NEON pipeline.... i assumed that means 1 FMAC per cycle....

Ref: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344j/BCGEIHDJ.html

A restriction that applies to VFP instructions executing in the NFP pipeline is that instruction results cannot be forwarded early to subsequent instructions. Each VFP instruction takes 7 cycles to execute in the NFP pipeline because of this restriction.

I did not check myself how bad that is, but that doesn't sound good.

BTW congratulations on the getting a Beagleboard from the contest.

Thanks! That QEMUonARM project will be difficult, I probably want too much, but that wouldn't be fun otherwise

 

[Adventus]

I did not check myself how bad that is, but that doesn't sound good.

Ouch, that certainly explains the poor nbench results we were getting. I can't see why the compiler doesn't just generate equivalent pure NEON instructions then, you get the same number of registers and losing predication would no doubt be worth it.

Thanks! That QEMUonARM project will be difficult, I probably want too much, but that wouldn't be fun otherwise

Haha Yea, aiming high is probably a good way to get them to send a beagleboard though. I think my project is too small.... i've already done 75% of it.

 

[warmi]

I did not check myself how bad that is, but that doesn't sound good.

Ouch, that certainly explains the poor nbench results we were getting. I can't see why the compiler doesn't just generate equivalent pure NEON instructions then, you get the same number of registers and losing predication would no doubt be worth it.

It does on the latest iPhone ... as long as you are using floats and not doubles.

 

[Adventus]

It does on the latest iPhone ... as long as you are using floats and not doubles.

Do you know what compiler they're using? is it mainline GCC or something propriety? I haven't tested this on the latest CS2009q1 release, maybe it's changed.

 

[darkblu]

Do you know what compiler they're using? is it mainline GCC or something propriety? I haven't tested this on the latest CS2009q1 release, maybe it's changed.

i strongly doubt it's a mainline compiler. apple never use mainline, they always have their own branches of gcc mainline revisions, usually a couple of minor revisions older than the 'gcc of the day' linuxes use. i don't have sdk3x installed yet, but i'm willing to guess the compiler there is something along 4.2

 

[warmi]

Yeah, it is GCC 4.2

PS.
Actually, it tends to generate Neon instructions mixed with VFP ones.

 

[Adventus]

Finally downloaded the CS2009q1 release and it appears to support hardfp via -mfloat-abi=hard, maybe i should recommend this compiler.... have there been any significant bugs reported?

At the moment i think if your getting bad floating point performance its almost always due to the compiler, it very rarely produces NEON instructions (only when very obvious vectorizable code is encountered). It might be worthwhile investigating the iPhone GCC branch.

 

[darkblu]

just stopping by to say that apparently gcc's ARM/hard_vfp_branch is getting trunk'ed these days. let the festivities begin! ; )

 

[ldesnogu]

Congratulations to Adventus for winning a Beagle

 

[darkblu]

there was a dog pageant Adventus participated in with a beagle?

oh, winning a beagle..