940 Clockspeed Control

[Pickle]

Any one know how to adjust the second core 940's clockspeed?

 

[Klepto]

I read about this somewhere a long time ago, either in the ARM docs or in the (terribly written) Magiceyes docs. I can't remember where exactly, it wasn't easy to find. While you wait on someone who actually knows answering you may want to try reading chapter 5 of this, it seems relevant.

 

[Pickle]

I read about this somewhere a long time ago, either in the ARM docs or in the (terribly written) Magiceyes docs. I can't remember where exactly, it wasn't easy to find. While you wait on someone who actually knows answering you may want to try reading chapter 5 of this, it seems relevant.


Thanks I will look at that.
The only app ive known to control the clock of the 940 was egoboo.

 

[Pickle]

I think your doc has helped. I found this code in cpuctrl:

CODE

extern void set_920_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */
extern void set_DCLK_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */

void set_920_Div(unsigned short div)
{
unsigned short v;
v = MEM_REG[0x91c>>1] & (~0x3);
MEM_REG[0x91c>>1] = (div & 0x7) | v;
}

void set_DCLK_Div( unsigned short div )
{
unsigned short v;
v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)) );
MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
}



This divides the FCLK to generate a cock for the 920.
From the doc you gave me theres are 3 bits for the 940 also. It happens I want to underclock the 940.
QUOTE

Address : C000 091ch
Bit R/W Symbol Description Reset Value
[8:6] R/W DCLKDIV DCLK Clock Generation F-PLL Divide Set Value(N-1)
[5:3] R/W A940TFDIV A940T FCLK Clock Generation F-PLL Divide Set Value(N-1). 0x0
[2:0] R/W A920TFDIV A920T FCLK Clock Generation F-PLL Divide Set Value(N-1). 0x0



I think this might work:
CODE

void set_940_Div( unsigned short div )
{
unsigned short v;
v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 3)) );
MEM_REG[0x91c>>1] = ((div & 0x7) << 3) | v;
}

 

[notaz]

Keep in mind that both 920 and 940 share the same clock source, so when you overclock 920 you will affect 940 too. However those divisors you listed are separate, but they only give you rough control.

 

[Pickle]

Keep in mind that both 920 and 940 share the same clock source, so when you overclock 920 you will affect 940 too. However those divisors you listed are separate, but they only give you rough control.

Its all about the FCLK

Notaz, do you know of another way to do it? Id prefer to set the 940 to an precise freq, but it seems that isnt supported.

 

[Klepto]

I think your doc has helped.
Not my doc, I just posted the link on the gp2x wiki.
QUOTE
Id prefer to set the 940 to an precise freq, but it seems that isnt supported.
I've read over chapter 5 again (I must be a masochist) and I think you're right, precise independent clock settings are not supported.

Just out of interest, what are you trying to do? Can't you fake it in software or is this to do with power conservation?

 

[Pickle]

Not my doc, I just posted the link on the gp2x wiki.

Sorry I can see after reading it no one would want to claim writing it. :rolleyes:

I've read over chapter 5 again (I must be a masochist) and I think you're right, precise independent clock settings are not supported.

Just out of interest, what are you trying to do? Can't you fake it in software or is this to do with power conservation?

Just trying to save power if I can.

 

[Klepto]

Sorry I can see after reading it no one would want to claim writing it. :rolleyes:

That made me laugh... a lot

Just trying to save power if I can.
Depending on how many/few cycles you want to run on the 940T it might be worth periodically putting it in idle mode. This would of course require the use of an interrupt to bring it back out of it's idle state and so would be horribly inefficient. It's just an idea, I'm operating at (probably beyond) the limit of my knowledge here, but it's an interesting problem.

 

[notaz]

Yes there is some "go to low power mode and wait for interrupt" MCR instruction, I used it in PicoDrive. Check the ARM940 manual.

 

[Pickle]

Well I got the divide to work by using the code used for cpuctrl. So i tried 920=200 Mhz 940=100Mhz since a divede by 2 is the lowest divisor i could use. Its not fast enough to keep up. I can run the program normally at 180, so the 940 would need to be between 100 and 180.
Im stumped though how egoboo set the 940 clock. That came with 2 binaries one at 250 and another at 225.
It had to have used something other than the divider.
Oh well at least I can set the game to run at a standard freq all the time. I learned a bit too.

 

[notaz]

That came with 2 binaries one at 250 and another at 225.
It had to have used something other than the divider.

No it didn't, although it's author believed that writing to PLL register from 940 wound adjust only 940 clock, he was wrong. You can prove that by setting 920 clock to let's say 100Mhz, launching egoboo, and you will see it runs exactly the same as if you launched it with say 250MHz, because 940 code overrides clock for both CPUs.

 

[Pickle]

That came with 2 binaries one at 250 and another at 225.
It had to have used something other than the divider.

No it didn't, although it's author believed that writing to PLL register from 940 wound adjust only 940 clock, he was wrong. You can prove that by setting 920 clock to let's say 100Mhz, launching egoboo, and you will see it runs exactly the same as if you launched it with say 250MHz, because 940 code overrides clock for both CPUs.

Yeah Notaz that makes sense. I should have thought of that :rolleyes: .