Power Draw Due To Ram Extension.

[imec]

So, I know 256MB is a great thing but is there going to be a substantial power draw in return? I heard PoisonIV talking about it on Engadget and I think it's an important question. Are there any specs available for the new chips (the people at the Beagleboard forum probably know something about it)?

Yes, I realize it's a pretty ridiculous question because the Pandora already has such great battery life but I'm sure people who have sent out their preorders are probably somewhat interested.

 

[PSyMastR]

I'de say knock an hour or two off the battery life. That's no fact, just a guess.

 

[PoisonedV]

Well obviously technology improves not just in power and efficiency, so I hope the power draw would be about the same, but I haven't seen any comparisons or links to statements about power draw of the two. even so, RAM may not draw much power in the first place.

 

[MWeston]

Some rough calculations with regulator losses puts the extra power drain at about 275mW when the chip is running full out (all banks accessed). At a mid-range battery voltage of 3.8V that puts the extra current drain at 72.4mAh so it's not a huge hit.

EDIT: It does translate to about a 45 minute loss on total battery life but that is if the chip was using it's maximum current the whole time the system was running which seems unlikely. It seems more like 20-25 minutes would be reasonable. At the kernel level, you could turn off the second 128MB and put it into self refresh if you really didn't want to use it. That sounds impractical and better battery life will come from managing the clock and core voltage as well as reducing backlight brightness when not necessary. Also, Pandora is designed to allow any part of the system not needed to be powered down to a level that uses almost no current.

 

[PoisonedV]

Ah, good to hear. really my only concern.

 

[BenTolputt]

Good to hear - thanks for the (relatively) quick response MWeston.

 

[lardman]

QUOTE
At the kernel level, you could turn off the second 128MB and put it into self refresh if you really didn't want to use it.


That's what the Psions used to do.

 

[mcobit]

Well, we heard, that the approx. runtime with snes emulation is about 8 hours. Did anyone test it with the wifi chip on? On my notebook at home, there is a significant reduction of battery life, when it uses wifi.

So how many hours of wifi-surfingtime will we have?

 

[Eversmile]

Some rough calculations with regulator losses puts the extra power drain at about 275mW when the chip is running full out (all banks accessed). At a mid-range battery voltage of 3.8V that puts the extra current drain at 72.4mAh so it's not a huge hit.

EDIT: It does translate to about a 45 minute loss on total battery life but that is if the chip was using it's maximum current the whole time the system was running which seems unlikely. It seems more like 20-25 minutes would be reasonable. At the kernel level, you could turn off the second 128MB and put it into self refresh if you really didn't want to use it. That sounds impractical and better battery life will come from managing the clock and core voltage as well as reducing backlight brightness when not necessary. Also, Pandora is designed to allow any part of the system not needed to be powered down to a level that uses almost no current.

mmm. That is a nice runtime...

 

[hereitcomes]

with double the ram we'll spend 20 mins less time waiting for apps to respond anyway

 

[greendots]

So this is a package on package on package?

 

[atomicthumbs]

Who cares about half an hour? The Pandora now has as much RAM as my (broken) laptop!

 

[maddis]

with double the ram we'll spend 20 mins less time waiting for apps to respond anyway

Well said

 

[benjiro]

with double the ram we'll spend 20 mins less time waiting for apps to respond anyway

You can also look at this the other way around.

Assume you lose 20min because of the add memory's extra power usage for programs that fit in the 128MB memory. But, those programs that don't fit in the 128MB memory ( ubuntu with lots open or heavy programs ), gain because it prevents swamping. At this point, your already gaining battery life, where as with the 128MB you where loosing it ( swap = write = cpu cycles wasted, power on the SD card wasted, etc ) ). There is a basic principle for the ARM ( hell, any CPU with powersaving ). Get the job done as fast as possible, so the CPU can downclock. So, any program that does not need to swap out anymore, eq battery life gain.

One thing i find a pity, is we don't know the details about the 256MB version. It might just be, that they shrunk the process to 45nm for the memory, instead of the 65nm ( we know for sure that the omap was made using 65nm ). Seeing as the memory is added on top of the cpu/gpu/dsp with POP. Might just as well be that there is almost no power drain.

MWeston, is there any more information available on the manufacturing process for those new 256MB versions? Ar they just basic "add more in the same space without any optimizations", or are the 256MB versions "different" then the 128MB version.

 

[Gilrad]

Considering he made it seem as though there are two distinct sections of 128mb ram chips, I would assume it would be the latter.

I wonder if the 'power down unnecessary components' function can be streamlined to basically have the P operate on 128mb of ram by default until it runs out, then switch on the other 128 chip instead of swapping.

 

[kloplop321]

interesting concept. that is kernel level, I think you should say it specifically to the Dev's handling the kernel

 

[benjiro]

Considering he made it seem as though there are two distinct sections of 128mb ram chips, I would assume it would be the latter.

I wonder if the 'power down unnecessary components' function can be streamlined to basically have the P operate on 128mb of ram by default until it runs out, then switch on the other 128 chip instead of swapping.

Seeing as how the nature of the ARM works, and other parts work, its going to be very "odd", if the system does not contain different banks / area blocks, that can power up or down when needed. Aka, 128MB = 8MB * 16blocks. You are using 17MB, so 3 blocks ( 24MB ) are powered up. Of course, its going to be a bitch to manage if a programmer tries to access a memory area outside of the available ( powered up ) blocks ( aka, the intelligent system for the memory might be forced to activate memory blocks when not needed to ). Unless they use the same system as SD's have to prevent wear & tear, but reverse ( forcing memory in the active blocks until they are full, and then power up the next block, and fill it ). Ofcourse, this is major speculation

Having only 2 different 128MB blocks is going to be odd. Something i have been thinking about: It also question the manufacturing process. If they only had the room voor 128MB ram / 256MB flash in the initial OMAP's, why do they now have the room to add the extra 128MB ram / 256MB flash. Seeing as the OMAP's chip dimensions are not exactly alterable ( limited working space ). In other words, they now must have used a smaller manufacturing process for the memory/flash of these OMAP's. Might just be a wild gamble, but thats all we got to go on. To much gambling, guesswork

 

[Svartalf]

I wonder if the 'power down unnecessary components' function can be streamlined to basically have the P operate on 128mb of ram by default until it runs out, then switch on the other 128 chip instead of swapping.

It's an interesting idea. Something that I don't think anyone's given much thought about- you start doing too many fancy things, though, and you run the risk of doing precisely the "wrong" things at the right time for at least some of the cases.

I'll ponder that thought while I'm digging through the code for some of the device issues I've been asked to look at.

 

[sindbad]

I'm pretty sure the extra power draw will be minimal. Even on a laptop, it's barely noticeable and the pandora's ram is very power efficient.

 

[Polossatik]

Considering he made it seem as though there are two distinct sections of 128mb ram chips, I would assume it would be the latter.

I wonder if the 'power down unnecessary components' function can be streamlined to basically have the P operate on 128mb of ram by default until it runs out, then switch on the other 128 chip instead of swapping.

Seeing as how the nature of the ARM works, and other parts work, its going to be very "odd", if the system does not contain different banks / area blocks, that can power up or down when needed. Aka, 128MB = 8MB * 16blocks. You are using 17MB, so 3 blocks ( 24MB ) are powered up. Of course, its going to be a bitch to manage if a programmer tries to access a memory area outside of the available ( powered up ) blocks ( aka, the intelligent system for the memory might be forced to activate memory blocks when not needed to ). Unless they use the same system as SD's have to prevent wear & tear, but reverse ( forcing memory in the active blocks until they are full, and then power up the next block, and fill it ). Ofcourse, this is major speculation

Having only 2 different 128MB blocks is going to be odd. Something i have been thinking about: It also question the manufacturing process. If they only had the room voor 128MB ram / 256MB flash in the initial OMAP's, why do they now have the room to add the extra 128MB ram / 256MB flash. Seeing as the OMAP's chip dimensions are not exactly alterable ( limited working space ). In other words, they now must have used a smaller manufacturing process for the memory/flash of these OMAP's. Might just be a wild gamble, but thats all we got to go on. To much gambling, guesswork


Might have look at the links provided here:
http://forum.openpandora.org/viewtopic.php...a&start=160

cheerio