Caanoo / WIZ Overclocking The Caanoo

[Lordus]

I recently got a Wiz and Caanoo and was playing around a bit with them.

I tried to set the clock speed by PLL0 in the way it was done on the Wiz, but anything below 233 and above 600 would crash.
I was wondering about this, so i investigated a bit and found that the default setup is different than that of the Wiz:

WIZ:
CLOCKMODEREG: 0x05010480 -> CLKSELBCLK=PLL1, CLKDIV1BCLK=1, CLKDIV2CPU0=3, ...
PLLSETREG0: 0x0024B000 -> PDIV=9,MDIV=176,SDIV=0
PLLSETREG1: 0x0024C402 -> PDIV=36,MDIV=196,SDIV=2

CAANOO:
CLOCKMODEREG: 0x043104C0 -> CLKSELBCLK=PLL0, CLKDIV1BCLK=4, CLKDIV2CPU0=4, ...
PLLSETREG0: 0x0024B000 -> PDIV=9,MDIV=176,SDIV=0
PLLSETREG1: 0x00285C01 -> PDIV=40,MDIV=92,SDIV=1

So the interesting difference is that on the Caanoo the system clock (BLCK) is derived from PLL0 instead of PLL1, and if you overclock via PLL0 the Wiz way, you overclock that as well.
I tried setting the Wiz's default values on the Caanoo, but that affects the display and ultimately results in a crash.
So i guess the difference in setup is due to the new display?

The display controller shows the follwing values on the Caanoo:
DPCCLKGEN0: 000000A3 -> CLKSRCSEL0=PLL1

I didn't try much more, but at the very least it doesn't seem to be as straightforward to overclock the Caanoo as it was on the Wiz,
or does anyone have any input and already successfully managed to overclock properly?

 

[Exophase]

A little further elaboration:

On both Wiz and Caanoo, default PLL0 is as follows: (27MHz * 176) / (9 * 1) = 528MHz
On Wiz, PLL1 = (27MHz * 196) / (36 * 4) = 36.75MHz
On Caanoo, PLL1 = (27MHz * 92) / (40 * 2) = 31.05MHz

On Wiz:

CPU0 = PLL0 / 1 (528MHz)
AHB = CPU0 / 3 (176MHz)
BCLK = PLL1 / 1 (36.75MHz)

On Caanoo:

CPU0 = PLL0 / 1 (528MHz)
AHB = CPU0 / 4 (132MHz)
BCLK = PLL0 / 4 (132MHz)

The Pollux datasheet actually says: "Be careful that the frequency of AHB bus clock must be lesser than133MHz.." So on Wiz, this is actually being violated and the memory bus is overclocked. All of this time I thought it was set to CPU / 4, not CPU / 3. If the memory clock can't keep up with it then there might not be much point in doing this.

BCLK is used for SRAM, NAND, I2S, USB, MLC (media layer controller), CSC (color space convertor).. maybe other things. In other words, almost all peripherals. DDR SDRAM isn't clocked on it, though. Chances are that different wait states had to be used on, ie, the NAND to make this work.

Incidentally, BCLK doesn't appear to feed into the DPC (display controller), which instead uses PLL0 or PLL1 directly. Here are some other values on Caanoo courtesy of Lordus:

DPCCLKENB: 0x0000000C
DPCCLKGEN0: 0x000000A3
DPCCLKGEN1: 0x0000000F

What this means is that the DPC0 uses PLL1 / 11 = 2.82MHz and DPC1 uses PLL1 uses "CLKGEN0 output", so I guess the same. I don't know what implications this has for TV out on either platform.

On Wiz the values are the same, meaning that DPC0 uses 3.34MHz. This isn't that strange when you consider on Wiz DPC0 is fed to an off-chip OLED controller instead of controlling a display directly. But I don't know all of the exact implications involved.

 

[notaz]

From what I remember on Wiz it is possible to overclock AHB a bit over 200MHz without problems, up to something like 220.

We need to get BCLK back on PLL1 somehow, otherwise the system won't be overclockable..

 

[Lordus]

I think it might work just using the dividers, i was able to overclock to a stable 660/792MHz,
by setting CLKDIV1BCLK and CLKDIV2CPU0 to 5/6, which effectively leaves the BCLK and AHB bus at the same speed as default.

 

[Exophase]

That's an option, but it definitely takes away a lot of the granularity in overclocking, and it means that performance won't scale with clock very well with the reduced AHB clock (have you tried it with only reducing the BCLK divider?).. so a Caanoo at 533MHz will perform worse than a Wiz at 533MHz (higher latency RAM, lower AHB speed), and at 792MHz worse by a wider margin. How much worse will have to be seen, I guess at least people will be able to comment when Pcsx4all is ported.

Still much better news.. hopefully 792MHz like this will be a lock for most people, I imagine it will be.

 

[Lordus]

I tried adapting only the BCLK divider, to make sure BCLK always stays <= 133 and that works fine.
The 792 were not really stable as i found out after posting, but 766 is with BCLK=PLL0/6 and AHB=PLL0/4 and RAM timings 3,8,4,1,1,1,1.

I say this with caution, as my benchmark might be flawed, but with this setup at 766MHz i get about the same results as on the Wiz clocked to 700MHz.

 

[Exophase]

That's good news, not having to sacrifice AHB clock further.. I wonder what the limiting factor is with 792.

What's your benchmark doing?

 

[Lordus]

It's just running an emulator at max speed, so there are some variables that might be different, like performance of the stock SDL lib etc, but it might be OK as a test for real world performance.

 

[Exophase]

I can give you Temper's code if you wanna try something without SDL. As a bonus you can also port Temper, if you want ;p

 

[Lordus]

When i disable everything that could interfere i get the same results, and that's good enough for me.

But anyway, i couldn't promise anything, but would give it a try to port Temper.

 

[Amon_Re]

I can give you Temper's code if you wanna try something without SDL. As a bonus you can also port Temper, if you want ;p

You sneaky devil you

 

[Lordus]

Edit: now correct values, which all but the last one run stable for me.

The steps are not linear, but every setting runs faster than the next lower one, and it seems to work quite well

  const HwDrvClkSetting HwDrvClkTable[] = 
  {
      // CPU,  PLL0,CPU div    AHB div    BCLK div    // CPU, AHB, BCLK
      {   66,  266, 4,         1,         2 },        //  66,  66, 133 MHz
      {  100,  400, 4,         1,         3 },        // 100, 100, 133 MHz
      {  133,  266, 2,         1,         2 },        // 133, 133, 133 MHz
      {  166,  666, 4,         1,         5 },        // 166, 167, 133 MHz
      {  200,  400, 2,         2,         3 },        // 200, 100, 133 MHz
      {  233,  933, 4,         2,         7 },        // 233, 117, 133 MHz
      {  266,  533, 2,         2,         4 },        // 266, 133, 133 MHz
      {  300,  900, 3,         2,         7 },        // 300, 150, 128 MHz
      {  333,  666, 2,         2,         5 },        // 333, 167, 133 MHz
      {  366,  733, 2,         3,         6 },        // 366, 122, 122 MHz
      {  400,  400, 1,         3,         3 },        // 400, 133, 133 MHz
      {  433,  866, 2,         3,         7 },        // 433, 144, 124 MHz
      {  466,  933, 2,         3,         7 },        // 466, 156, 133 MHz
      {  500,  500, 1,         3,         4 },        // 500, 166, 125 MHz
      {  533,  533, 1,         4,         4 },        // 533, 133, 133 MHz
      {  566, 1133, 2,         4,         9 },        // 566, 142, 126 MHz
      {  600,  600, 1,         4,         5 },        // 600, 150, 120 MHz
      {  633,  633, 1,         4,         5 },        // 633, 158, 127 MHz
      {  666,  666, 1,         4,         5 },        // 666, 167, 133 MHz
      {  700,  700, 1,         4,         6 },        // 700, 175, 117 MHz
      {  733,  733, 1,         4,         6 },        // 733, 183, 122 MHz
      {  766,  766, 1,         4,         6 },        // 766, 192, 128 MHz
      {  800,  800, 1,         5,         6 },        // 800, 160, 133 MHz
  };

The documentation says, the AHB divider CLKDIV2CPU0 can just be in the range 2-16, but setting it 1 works, and runs faster than setting it to 2, so i am not sure about that.

 

[Lordus]

I made a modified experimental version of pollux_set for the Caanoo, which allows to set the ram timings and clock from 66MHz-800MHz.

The cpu clock will be set in 33MHz intervals like in the table shown in my previous post, so if you set the clock to 620 for example it will use the 633MHz setting etc.

The code checks if BCLK is really set to PLL0 first, and if not, uses the Wiz method to overclock (in case the PLL setup is ever changed).

Source is included. Use it at your own risk!

Running this before anything that tries to set the clock itself in the old Wiz way (like the currently available MAME version) is not recommended.

Edit: If you download this, be aware, that it won't work with the new coming firmware anymore.

 

[Exophase]

Looks like some really good work, thanks Lordus.

I wonder how much impact AHB speed really has in practice. Is the SDRAM clocked directly off of AHB afterall? I meant to check that and forgot to.

If I send you a cache miss timing test are you willing to run it at all those clock speeds too?

 

[Lordus]

No problem, I'd run the test of course. I am interested in that myself.

 

[simon(gph)]

Hi,

I'm a staff of GPH R&D and in charge of technical support.
We prepare new official firmware and release at 15 Sep.
Refer to following changlog.

1. for overclocking

PLL0 = 530.55Mhz (p=20, m=393, s=0) Changed for IIS(Sound Interface) Source Clock.
AHB = PLL0 / 4
PLL1 = 132.75Mhz (p=6, m=59, s=1) Changed for stability of Caanoo.
BCLK = PLL1
IIS = PLL0/n

2. add kernel compile option

CONFIG_OABI_COMPAT

3. touchscreen sampling rate (Thanks, Juan)

100hz -> 50hz (WIZ=50hz) Changed for Performance.

4. Fix NAND timing when overclocking.


If you want to try with it, send me e-mail (simon@gp2x.com).
But i don't want publish it before release.

Thanks,
Simon.

 

[RupeeClock]

Hiya Simon.
Can I ask, when will the Caanoo support the TV-out adapter, will it require an added option in the firmware?
I'd also like to know, will the Caanoo support autobooting in the future? It was one of my favourite features for the GP2X and the Wiz, because it allowed me to load Gmenu2X as an alternative front-end.

Thanks.

 

[notaz]

1. for overclocking

PLL0 = 530.55Mhz (p=20, m=393, s=0) Changed for IIS(Sound Interface) Source Clock.
AHB = PLL0 / 4
PLL1 = 132.75Mhz (p=6, m=59, s=1) Changed for stability of Caanoo.
BCLK = PLL1

That's good, sounds like old overclocking method will work with this.

IIS = PLL0/n

Why?? Won't that cause sound speedup when overclocking? This will break all programs that don't use dedicated threads to generate sound.

If you want to try with it, send me e-mail (simon@gp2x.com).
But i don't want publish it before release.

Can you publish the kernel source? Linux kernel is licensed under GPLv2, which requires making the source available when binaries are released.

 

[SiENcE]

2. add kernel compile option

CONFIG_OABI_COMPAT

Does this mean, we can run WIZ applications on Caanoo?

 

[crow_riot]

2. add kernel compile option

CONFIG_OABI_COMPAT

Does this mean, we can run WIZ applications on Caanoo?

i think that's the reason, yes. but i dont see any use of that OABI mode, because the button IDs returned are totally different from what the Wiz used. So running a wiz app might work then, but it makes no sense because the buttons are just wrong then.