GP2X Can Anyone (with Gph's Toolchain 2.95 For Linux) Compile This?


rlyeh

rlyeh

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Can anyone compile this kernel module using GPH's toolchain 2.95 for linux?

I know I could install cygwin, then gcc, then arm-linux toolchain, then configure it and get this source finally compiled... but I'm lazy you know.

Btw, since it has never been compiled before it's probably full of bugs & syntax errors :) Sorry for that.

Code: 
/* Kernel device driver for Minimal Library SDK. 
   Based on previous work by Squidge and NK.
   Written by rlyeh, (c) 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif

#define MINIMAL_I2C_WRITE			 0
#define MINIMAL_I2C_READ			  1
#define MINIMAL_MMU_INSTALLHACK	   2
#define MINIMAL_MMU_FLUSHCACHE		3

#define MINIMAL_MMU_R001  0x100

#define MINIMAL_MMU_R100  0x101
#define MINIMAL_MMU_W100  0x102
#define MINIMAL_MMU_R200  0x103
#define MINIMAL_MMU_W200  0x104
#define MINIMAL_MMU_R300  0x105
#define MINIMAL_MMU_W300  0x106
#define MINIMAL_MMU_R500  0x107
#define MINIMAL_MMU_W500  0x108
#define MINIMAL_MMU_R501  0x109
#define MINIMAL_MMU_W501  0x10a
#define MINIMAL_MMU_R600  0x10b
#define MINIMAL_MMU_W600  0x10c

#define MINIMAL_MMU_W750  0x10d
#define MINIMAL_MMU_W760  0x10e
#define MINIMAL_MMU_W770  0x10f
#define MINIMAL_MMU_W751  0x110
#define MINIMAL_MMU_W7131 0x111
#define MINIMAL_MMU_W761  0x112
#define MINIMAL_MMU_W7101 0x113
#define MINIMAL_MMU_W7141 0x114
#define MINIMAL_MMU_W7102 0x115
#define MINIMAL_MMU_W7104 0x116
#define MINIMAL_MMU_W7142 0x117
#define MINIMAL_MMU_W704  0x118

#define MINIMAL_MMU_W870  0x119
#define MINIMAL_MMU_W850  0x11a
#define MINIMAL_MMU_W851  0x11b
#define MINIMAL_MMU_W860  0x11c
#define MINIMAL_MMU_W861  0x11d
 
#define MINIMAL_MMU_R900  0x11e
#define MINIMAL_MMU_W900  0x11f
#define MINIMAL_MMU_R901  0x120
#define MINIMAL_MMU_W901  0x121

#define MINIMAL_MMU_R1000 0x122
#define MINIMAL_MMU_W1000 0x123
#define MINIMAL_MMU_R1001 0x124
#define MINIMAL_MMU_W1001 0x125

#define MINIMAL_MMU_R1300 0x126
#define MINIMAL_MMU_W1300 0x127

#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
 { arg = ag; asm volatile( \
 	"stmdb sp!, {r0}\n\t" \
	"mov	r0, %0\n\t" \
	"mcr	p15, 0, r0, " act "\n\t" \
	"ldmia sp!, {r0}\n\t": "=r" (arg)); }

#define MMU_READ(act,rt) \
 { asm volatile( \
 	"stmdb sp!, {r0}\n\t" \
	"mrc p15, 0, r0, " act "\n\t" \
	"mov %0, r0\n\t" \
	"ldmia sp!, {r0}\n\t": "=r"(rt)); }

extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;


static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
 return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
 return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{ 
 int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); } 
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); } 

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));
 
CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg)); 
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg)); 

 if(cmd == MINIMAL_MMU_FLUSHCACHE)
 {
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
 }

 if(cmd == MINIMAL_I2C_WRITE)
 {
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
 }

 if(cmd == MINIMAL_I2C_READ)
 { 
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
 }

 if(cmd == MINIMAL_MMU_INSTALLHACK)
 {
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  pgtable = __va(ttb);

  for (i = 0; i < 4096; i ++) if ( (pgtable[i] & 3) == 1 ) {
   cpt = __va(pgtable[i] & 0xfffffc00);

  for (j = 0; j < 256; j ++)
   if ( (cpt[j] & 0xff00000f) == 0x02000002 || 
		(cpt[j] & 0xff00000f) == 0x03000002 ) {
	// set C and B bits in upper 32MB memory area...
	cpt[j] |= 0xFFC;
	}
  }

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
 }
 
 return -EINVAL;
}

static struct file_operations minimal_fops = 
{
 owner:		  THIS_MODULE,
 ioctl:		  minimal_ioctl,
 open:		   minimal_open,
 release:		minimal_release,
};

static struct miscdevice minimal = 
{
	255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
 misc_register(&minimal);
 return 0;
}

static void __exit minimal_exit(void)
{
 misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");
 
Without more understanding of what you want here is the results:
Code: 
[gwmiller@uniserv stuff]$ make
arm-linux-gcc -D__KERNEL__ -I/home/gwmiller/gp2x/kernelDev/2.0.0/include -O2 -fno-strict-aliasing -fno-common -Uarm -fno-common -pipe -D__LINUX_ARM_ARCH__=4 -mtune=arm9tdmi -mshort-load-bytes -msoft-float -Uarm -DLinux -DMODULE -DMODVERSIONS -DEXPORT_SYMTAB -DDBG -Wall -Wstrict-prototypes -Wno-trigraphs -I/usr/local/arm-dev/include  -c -o foo.o foo.c
foo.c: In function `minimal_ioctl':
foo.c:116: warning: implicit declaration of function `copy_from_user'
foo.c:116: output operand constraint lacks `='
foo.c:117: output operand constraint lacks `='
foo.c:118: output operand constraint lacks `='
foo.c:119: output operand constraint lacks `='
foo.c:120: output operand constraint lacks `='
foo.c:121: output operand constraint lacks `='
foo.c:122: output operand constraint lacks `='
foo.c:123: output operand constraint lacks `='
foo.c:124: output operand constraint lacks `='
foo.c:125: output operand constraint lacks `='
foo.c:126: output operand constraint lacks `='
foo.c:127: output operand constraint lacks `='
foo.c:132: output operand constraint lacks `='
foo.c:134: output operand constraint lacks `='
foo.c:136: output operand constraint lacks `='
foo.c:138: output operand constraint lacks `='
foo.c:140: output operand constraint lacks `='
foo.c:142: output operand constraint lacks `='
foo.c:144: output operand constraint lacks `='
foo.c:145: output operand constraint lacks `='
foo.c:146: output operand constraint lacks `='
foo.c:147: output operand constraint lacks `='
foo.c:148: output operand constraint lacks `='
foo.c:151: output operand constraint lacks `='
foo.c:153: output operand constraint lacks `='
foo.c:156: output operand constraint lacks `='
foo.c:158: output operand constraint lacks `='
foo.c:161: output operand constraint lacks `='
foo.c:197: parse error before `0x103'
foo.c:213: parse error before `0x116'
foo.c:214: parse error before `0x119'
foo.c:194: warning: `ttb' might be used uninitialized in this function
make: *** [foo.o] Error 1

I assume if I had copy from user this would reduce the errors.
 
"copy_from_user" is in asm/uaccess.h so I #included it so we are now at:
Code: 
[gwmiller@uniserv stuff]$ make
arm-linux-gcc -D__KERNEL__ -I/home/gwmiller/gp2x/kernelDev/2.0.0/include -O2 -fno-strict-aliasing -fno-common -Uarm -fno-common -pipe -D__LINUX_ARM_ARCH__=4 -mtune=arm9tdmi -mshort-load-bytes -msoft-float -Uarm -DLinux -DMODULE -DMODVERSIONS -DEXPORT_SYMTAB -DDBG -Wall -Wstrict-prototypes -Wno-trigraphs -I/usr/local/arm-dev/include  -c -o foo.o foo.c
foo.c: In function `minimal_ioctl':
foo.c:117: output operand constraint lacks `='
foo.c:118: output operand constraint lacks `='
foo.c:119: output operand constraint lacks `='
foo.c:120: output operand constraint lacks `='
foo.c:121: output operand constraint lacks `='
foo.c:122: output operand constraint lacks `='
foo.c:123: output operand constraint lacks `='
foo.c:124: output operand constraint lacks `='
foo.c:125: output operand constraint lacks `='
foo.c:126: output operand constraint lacks `='
foo.c:127: output operand constraint lacks `='
foo.c:128: output operand constraint lacks `='
foo.c:133: output operand constraint lacks `='
foo.c:135: output operand constraint lacks `='
foo.c:137: output operand constraint lacks `='
foo.c:139: output operand constraint lacks `='
foo.c:141: output operand constraint lacks `='
foo.c:143: output operand constraint lacks `='
foo.c:145: output operand constraint lacks `='
foo.c:146: output operand constraint lacks `='
foo.c:147: output operand constraint lacks `='
foo.c:148: output operand constraint lacks `='
foo.c:149: output operand constraint lacks `='
foo.c:152: output operand constraint lacks `='
foo.c:154: output operand constraint lacks `='
foo.c:157: output operand constraint lacks `='
foo.c:159: output operand constraint lacks `='
foo.c:162: output operand constraint lacks `='
foo.c:198: parse error before `0x103'
foo.c:214: parse error before `0x116'
foo.c:215: parse error before `0x119'
foo.c:195: warning: `ttb' might be used uninitialized in this function
make: *** [foo.o] Error 1
[gwmiller@uniserv stuff]$

The macro CMDW is causing the error but I am not sure what you intended so I do not know what to modify.

Current first line of error:
Code: 
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));

Macro is defined as: (spacing added for clarity)
Code: 
#define CMDW(c, a) if(cmd == (c)) { \
													  copy_from_user(&arg, (int *)argm, sizeof(int)); \
													  {a}; \
													  return (1); \
													 }

Maybe you wanted to assign 'a' to something?
 
That's valid... 'a' is an expansion of the second argument to the macro.

The problem is MMU_WRITE I think.


CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));

expands to:

CMDW(0x116, { arg = arg; asm volatile( \
"stmdb sp!, {r0}\n\t" \
"mov r0, %0\n\t" \
"mcr p15, 0, r0, " "c7,c10,4" "\n\t" \
"ldmia sp!, {r0}\n\t": "=r" (arg)); } );

(which in turn expands to:

if(cmd == (0x116)) {
copy_from_user(&arg, (int *)argm, sizeof(int));
{{ arg = arg; asm volatile("stmdb sp!, {r0}\n\tmov r0, %0\n\tmcr p15, 0, r0,c7,c10,4\n\tldmia sp!, {r0}\n\t": "=r" (arg)); }};
return (1);
}

The error you're getting is an asm error. Unfortunately I don't know ARM assembly so can't see the error there, but I bet it has something to do with the =r clause somehow.
 
Ok changing the macro to:
Code: 
#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
		"stmdb sp!, {r0}\n\t" \
		"mov	r0, %0\n\t" \
		"mcr	15, 0, r0, "##act##"\n\t" \
		"ldmia sp!, {r0}\n\t": "=r"(arg)); }
Fixed the syntax error but I have only done external ARM/THUMB assembly so I am unsure what it does.

So at this point the errors are:
Code: 
[gwmiller@uniserv stuff]$ make
arm-linux-gcc -D__KERNEL__ -I/home/gwmiller/gp2x/kernelDev/2.0.0/include -O2 -fno-strict-aliasing -fno-common -Uarm -fno-common -pipe -D__LINUX_ARM_ARCH__=4 -mtune=arm9tdmi -mshort-load-bytes -msoft-float -Uarm -DLinux -DMODULE -DMODVERSIONS -DEXPORT_SYMTAB -DDBG -Wall -Wstrict-prototypes -Wno-trigraphs -I/usr/local/arm-dev/include  -c -o foo.o foo.c
foo.c: In function `minimal_ioctl':
foo.c:198: parse error before `0x103'
foo.c:214: parse error before `0x116'
foo.c:215: parse error before `0x119'
foo.c:195: warning: `ttb' might be used uninitialized in this function
make: *** [foo.o] Error 1
Which is the MMU_READ macro ...
 
Well the issue is how the macro is used but I don't have any information on what the lines of code should do so there is little I can do to change the code. All other lines that us these macro's pass a literal string as the first argument and these send a numeric constant. Here are the lines:
Code: 
  // get the pointer to the translation table base...
*  MMU_READ(MINIMAL_MMU_R200, ttb);

  pgtable = __va(ttb);

 .
 .
 .

  // drain the write buffer and flush the tlb caches...
*  MMU_WRITE(MINIMAL_MMU_W7104, 0);
*  MMU_WRITE(MINIMAL_MMU_W870,  0);

Any suggestions for what they should really be?
 
Here is code that compiles and builds a module but the changes I made to make it compile are completely suspect since I do not understand what the lines were meant to do:
Code: 
/* Kernel device driver for Minimal Library SDK.
   Based on previous work by Squidge and NK.
   Written by rlyeh, (c) 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>
#include <asm/uaccess.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif

#define MINIMAL_I2C_WRITE			 0
#define MINIMAL_I2C_READ			  1
#define MINIMAL_MMU_INSTALLHACK	   2
#define MINIMAL_MMU_FLUSHCACHE		3

#define MINIMAL_MMU_R001  0x100

#define MINIMAL_MMU_R100  0x101
#define MINIMAL_MMU_W100  0x102
#define MINIMAL_MMU_R200  0x103
#define MINIMAL_MMU_W200  0x104
#define MINIMAL_MMU_R300  0x105
#define MINIMAL_MMU_W300  0x106
#define MINIMAL_MMU_R500  0x107

#define MINIMAL_MMU_W500  0x108
#define MINIMAL_MMU_R501  0x109
#define MINIMAL_MMU_W501  0x10a
#define MINIMAL_MMU_R600  0x10b
#define MINIMAL_MMU_W600  0x10c

#define MINIMAL_MMU_W750  0x10d
#define MINIMAL_MMU_W760  0x10e
#define MINIMAL_MMU_W770  0x10f
#define MINIMAL_MMU_W751  0x110
#define MINIMAL_MMU_W7131 0x111
#define MINIMAL_MMU_W761  0x112
#define MINIMAL_MMU_W7101 0x113
#define MINIMAL_MMU_W7141 0x114
#define MINIMAL_MMU_W7102 0x115
#define MINIMAL_MMU_W7104 0x116
#define MINIMAL_MMU_W7142 0x117
#define MINIMAL_MMU_W704  0x118

#define MINIMAL_MMU_W870  0x119
#define MINIMAL_MMU_W850  0x11a
#define MINIMAL_MMU_W851  0x11b
#define MINIMAL_MMU_W860  0x11c
#define MINIMAL_MMU_W861  0x11d

#define MINIMAL_MMU_R900  0x11e
#define MINIMAL_MMU_W900  0x11f
#define MINIMAL_MMU_R901  0x120
#define MINIMAL_MMU_W901  0x121

#define MINIMAL_MMU_R1000 0x122
#define MINIMAL_MMU_W1000 0x123
#define MINIMAL_MMU_R1001 0x124
#define MINIMAL_MMU_W1001 0x125

#define MINIMAL_MMU_R1300 0x126
#define MINIMAL_MMU_W1300 0x127

#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
		"stmdb sp!, {r0}\n\t" \
		"mov	r0, %0\n\t" \
		"mcr	15, 0, r0, "##act##"\n\t" \
		"ldmia sp!, {r0}\n\t": "=r"(arg)); }

#define MMU_READ(act,rt) \
{ asm volatile( \
		"stmdb sp!, {r0}\n\t" \
		"mrc p15, 0, r0, "##act##"\n\t" \
		"mov %0, r0\n\t" \
		"ldmia sp!, {r0}\n\t": "=r"(rt)); }

extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;


static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{
int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); }
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); }

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));

CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg));
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg));

if(cmd == MINIMAL_MMU_FLUSHCACHE)
{
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
}

if(cmd == MINIMAL_I2C_WRITE)
{
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
}

if(cmd == MINIMAL_I2C_READ)
{
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
//  MMU_READ(MINIMAL_MMU_R200, ttb);
  CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ttb));

  pgtable = __va(ttb);

  for (i = 0; i < 4096; i ++) if ( (pgtable[i] & 3) == 1 ) {
   cpt = __va(pgtable[i] & 0xfffffc00);

  for (j = 0; j < 256; j ++)
   if ( (cpt[j] & 0xff00000f) == 0x02000002 ||
		(cpt[j] & 0xff00000f) == 0x03000002 ) {
		// set C and B bits in upper 32MB memory area...
		cpt[j] |= 0xFFC;
		}
  }

  // drain the write buffer and flush the tlb caches...
//  MMU_WRITE(MINIMAL_MMU_W7104, 0);
  CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",0));
//  MMU_WRITE(MINIMAL_MMU_W870,  0);
  CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", 0));

  return 1;
}

return -EINVAL;
}

static struct file_operations minimal_fops =
{
owner:		  THIS_MODULE,
ioctl:		  minimal_ioctl,
open:		   minimal_open,
release:		minimal_release,
};

static struct miscdevice minimal =
{
	255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
misc_register(&minimal);
return 0;
}

static void __exit minimal_exit(void)
{
misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");

The module file can be pulled from http://www.ivrtech.net/files/stuff.o, as is this file may trash your system if the changes I made are not correct. I hope that rlyeh can give some guidance as to the correctness of my changes.
 
Thanks for the object file, but the .o won't work right yet! The MMU_READ() changes you did in the switch section are wrong, and MMU_WRITE() needed a 'p15' instead of '15' too (apart from including uaccess.h! thanks for that tip). It's hard to figure out errors and warnings with no compiling!

Can you compile the following source? (it's apparently right debugged now).

Code: 
/* Kernel device driver for Minimal Library SDK.
   Based on previous work by Squidge and NK.
   Written by rlyeh, (c) 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>
#include <asm/uaccess.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif

/* declarations for I2C IOCTLs */
extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;

/* our IOCTLs consts */
#define MINIMAL_I2C_WRITE			0x0
#define MINIMAL_I2C_READ			 0x1
#define MINIMAL_MMU_INSTALLHACK	  0x2
#define MINIMAL_MMU_FLUSHCACHE	   0x3
#define MINIMAL_MMU_R001			 0x100
#define MINIMAL_MMU_R100			 0x101
#define MINIMAL_MMU_W100			 0x102
#define MINIMAL_MMU_R200			 0x103
#define MINIMAL_MMU_W200			 0x104
#define MINIMAL_MMU_R300			 0x105
#define MINIMAL_MMU_W300			 0x106
#define MINIMAL_MMU_R500			 0x107
#define MINIMAL_MMU_W500			 0x108
#define MINIMAL_MMU_R501			 0x109
#define MINIMAL_MMU_W501			 0x10a
#define MINIMAL_MMU_R600			 0x10b
#define MINIMAL_MMU_W600			 0x10c
#define MINIMAL_MMU_W750			 0x10d
#define MINIMAL_MMU_W760			 0x10e
#define MINIMAL_MMU_W770			 0x10f
#define MINIMAL_MMU_W751			 0x110
#define MINIMAL_MMU_W7131			0x111
#define MINIMAL_MMU_W761			 0x112
#define MINIMAL_MMU_W7101			0x113
#define MINIMAL_MMU_W7141			0x114
#define MINIMAL_MMU_W7102			0x115
#define MINIMAL_MMU_W7104			0x116
#define MINIMAL_MMU_W7142			0x117
#define MINIMAL_MMU_W704			 0x118
#define MINIMAL_MMU_W870			 0x119
#define MINIMAL_MMU_W850			 0x11a
#define MINIMAL_MMU_W851			 0x11b
#define MINIMAL_MMU_W860			 0x11c
#define MINIMAL_MMU_W861			 0x11d
#define MINIMAL_MMU_R900			 0x11e
#define MINIMAL_MMU_W900			 0x11f
#define MINIMAL_MMU_R901			 0x120
#define MINIMAL_MMU_W901			 0x121
#define MINIMAL_MMU_R1000			0x122
#define MINIMAL_MMU_W1000			0x123
#define MINIMAL_MMU_R1001			0x124
#define MINIMAL_MMU_W1001			0x125
#define MINIMAL_MMU_R1300			0x126
#define MINIMAL_MMU_W1300			0x127
#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mov	r0, %0\n\t" \
	"mcr	p15, 0, r0, " act "\n\t" \
	"ldmia sp!, {r0}\n\t": "=r" (arg)); }

#define MMU_READ(act,rt) \
{ asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mrc p15, 0, r0, " act "\n\t" \
	"mov %0, r0\n\t" \
	"ldmia sp!, {r0}\n\t": "=r"(rt)); }



static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
 return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
 return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{
int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); }
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); }

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));

CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg));
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg));

if(cmd == MINIMAL_MMU_FLUSHCACHE)
{
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
 return 1;
}

if(cmd == MINIMAL_I2C_WRITE)
{
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
}

if(cmd == MINIMAL_I2C_READ)
{
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xfe00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

 return -EINVAL;
}

static struct file_operations minimal_fops =
{
 owner:		  THIS_MODULE,
 ioctl:		  minimal_ioctl,
 open:		   minimal_open,
 release:		minimal_release,
};

static struct miscdevice minimal =
{
 255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
 misc_register(&minimal);
 return 0;
}

static void __exit minimal_exit(void)
{
 misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");
 
try this;
http://gnostic.lryiu.com/gp2x/minimmu.rar

OR (structure-size-boundary=8 version);
http://gnostic.lryiu.com/gp2x/minimmu2.rar

rlyeh posted on Nov 11 2006 said:
Thanks for the object file, but the .o won't work right yet! The MMU_READ() changes you did in the switch section are wrong, and MMU_WRITE() needed a 'p15' instead of '15' too (apart from including uaccess.h! thanks for that tip). It's hard to figure out errors and warnings with no compiling!

Can you compile the following source? (it's apparently right debugged now).
Click to expand...
 
Last edited by a moderator:
Thanks GaryMiller & Gnostic for the .o
It's getting better, but can you guys compile now this one?

Thanks in advance so much :)

Code: 
/* Kernel device driver for Minimal Library SDK.
   Based on previous work by Squidge and NK.
   Written by rlyeh, © 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>
#include <asm/uaccess.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif

/* declarations for I2C IOCTLs */
#if 0
extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;
#endif

/* our IOCTLs consts */
#define MINIMAL_I2C_WRITE			0x0
#define MINIMAL_I2C_READ			 0x1
#define MINIMAL_MMU_FLUSHCACHE	   0x2
#define MINIMAL_MMU_INSTALLHACK	  0x3
#define MINIMAL_MMU_INSTALLHACK_32   0x4
#define MINIMAL_MMU_INSTALLHACK_48   0x5
#define MINIMAL_MMU_R001			 0x100
#define MINIMAL_MMU_R100			 0x101
#define MINIMAL_MMU_W100			 0x102
#define MINIMAL_MMU_R200			 0x103
#define MINIMAL_MMU_W200			 0x104
#define MINIMAL_MMU_R300			 0x105
#define MINIMAL_MMU_W300			 0x106
#define MINIMAL_MMU_R500			 0x107
#define MINIMAL_MMU_W500			 0x108
#define MINIMAL_MMU_R501			 0x109
#define MINIMAL_MMU_W501			 0x10a
#define MINIMAL_MMU_R600			 0x10b
#define MINIMAL_MMU_W600			 0x10c
#define MINIMAL_MMU_W750			 0x10d
#define MINIMAL_MMU_W760			 0x10e
#define MINIMAL_MMU_W770			 0x10f
#define MINIMAL_MMU_W751			 0x110
#define MINIMAL_MMU_W7131			0x111
#define MINIMAL_MMU_W761			 0x112
#define MINIMAL_MMU_W7101			0x113
#define MINIMAL_MMU_W7141			0x114
#define MINIMAL_MMU_W7102			0x115
#define MINIMAL_MMU_W7104			0x116
#define MINIMAL_MMU_W7142			0x117
#define MINIMAL_MMU_W704			 0x118
#define MINIMAL_MMU_W870			 0x119
#define MINIMAL_MMU_W850			 0x11a
#define MINIMAL_MMU_W851			 0x11b
#define MINIMAL_MMU_W860			 0x11c
#define MINIMAL_MMU_W861			 0x11d
#define MINIMAL_MMU_R900			 0x11e
#define MINIMAL_MMU_W900			 0x11f
#define MINIMAL_MMU_R901			 0x120
#define MINIMAL_MMU_W901			 0x121
#define MINIMAL_MMU_R1000			0x122
#define MINIMAL_MMU_W1000			0x123
#define MINIMAL_MMU_R1001			0x124
#define MINIMAL_MMU_W1001			0x125
#define MINIMAL_MMU_R1300			0x126
#define MINIMAL_MMU_W1300			0x127
#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mov	r0, %0\n\t" \
	"mcr	p15, 0, r0, " act "\n\t" \
	"ldmia sp!, {r0}\n\t": "=r" (arg)); }

#define MMU_READ(act,rt) \
{ asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mrc p15, 0, r0, " act "\n\t" \
	"mov %0, r0\n\t" \
	"ldmia sp!, {r0}\n\t": "=r"(rt)); }



static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
 return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
 return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{
int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); }
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); }

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));

CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg));
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg));

if(cmd == MINIMAL_MMU_FLUSHCACHE)
{
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
  return 1;
}

/*
if(cmd == MINIMAL_I2C_WRITE)
{
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
}

if(cmd == MINIMAL_I2C_READ)
{
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
}
*/

if(cmd == MINIMAL_MMU_INSTALLHACK_32)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xff00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK_48)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xff00000f) == 0x03000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xfe00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

 return -EINVAL;
}

static struct file_operations minimal_fops =
{
 owner:		  THIS_MODULE,
 ioctl:		  minimal_ioctl,
 open:		   minimal_open,
 release:		minimal_release,
};

static struct miscdevice minimal =
{
 255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
 misc_register(&minimal);
 return 0;
}

static void __exit minimal_exit(void)
{
 misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");
 
Done ... same place as before ..

Code: 
[gwmiller@uniserv stuff]$ rm foo.c
[gwmiller@uniserv stuff]$ vi foo.c
[gwmiller@uniserv stuff]$ make
arm-linux-gcc -D__KERNEL__ -I/home/gwmiller/gp2x/kernelDev/2.0.0/include -O2 -fno-strict-aliasing -fno-common -Uarm -fno-common -pipe -D__LINUX_ARM_ARCH__=4 -mtune=arm9tdmi -mshort-load-bytes -msoft-float -Uarm -DLinux -DMODULE -DMODVERSIONS -DEXPORT_SYMTAB -DDBG -Wall -Wstrict-prototypes -Wno-trigraphs -I/usr/local/arm-dev/include  -c -o foo.o foo.c
arm-linux-ld -r foo.o -o stuff.o
[gwmiller@uniserv stuff]$ cp stuff.o ~/www/files
[gwmiller@uniserv stuff]$
 
Got another source to compile :p
Thanks in advance

This one is probably full of syntax errors. Please post the warnings / errors here to let me fix them.

Code: 
/* Kernel device driver for Minimal Library SDK.
   Based on previous work by Squidge and NK.
   Written by rlyeh, (c) 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>
#include <asm/uaccess.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif


/* declarations for I2C IOCTLs */
#if 1

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/delay.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;


#define SCCB_SCL_INPUT	set_gpio_ctrl(GPIO_SCL, GPIOMD_IN, GPIOPU_NOSET)
#define SCCB_SCL_OUTPUT	set_gpio_ctrl(GPIO_SCL, GPIOMD_OUT, GPIOPU_NOSET)
#define SCCB_SCL_LOW	write_gpio_bit(GPIO_SCL, 0)
#define SCCB_SCL_HIGH	write_gpio_bit(GPIO_SCL, 1)
#define SCCB_SCL_DATA	read_gpio_bit(GPIO_SCL)

#define SCCB_SDA_INPUT	set_gpio_ctrl(GPIO_SDA, GPIOMD_IN, GPIOPU_NOSET)
#define SCCB_SDA_OUTPUT	set_gpio_ctrl(GPIO_SDA, GPIOMD_OUT, GPIOPU_NOSET)
#define SCCB_SDA_LOW	write_gpio_bit(GPIO_SDA, 0)
#define SCCB_SDA_HIGH	write_gpio_bit(GPIO_SDA, 1)
#define SCCB_SDA_DATA	read_gpio_bit(GPIO_SDA)

#define SCCB_DELAY	I2C_delay()


#define i2c_stop() {SCCB_SCL_LOW; SCCB_SDA_LOW;}

#define i2c_start1 {SCCB_SDA_HIGH; SCCB_SCL_HIGH; SCCB_SCL_OUTPUT; SCCB_SDA_OUTPUT; SCCB_DELAY; i2c_stop();}
#define i2c_start2 {i2c_stop(); SCCB_SDA_OUTPUT;}
#define i2c_start3 {SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SDA_HIGH;}

#define i2c_start(x) {{ x } \
		i2c_start3; \
	SCCB_DELAY; SCCB_DELAY; SCCB_DELAY; \
	SCCB_SDA_LOW; SCCB_DELAY; SCCB_SCL_LOW;}

#define i2c_writeSlave(what) \
	{for( i=7; i>=0; i-- ) \
	{ if( (what) & (1<<i) ) SCCB_SDA_HIGH; else SCCB_SDA_LOW; \
	  SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SCL_LOW; } \
	SCCB_SDA_INPUT; \
	SCCB_DELAY; \
	SCCB_SCL_HIGH; \
	if( SCCB_SDA_DATA ) I2C_failed(); \
	SCCB_DELAY;}

#define i2c_end() \
	{i2c_stop(); SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SDA_HIGH; \
	SCCB_SCL_INPUT; SCCB_SDA_INPUT;}

int i2c_set;

int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

void I2C_delay( void )
{
 volatile int i, j, k;
 for(i=0;i<20;i++) for(j=0;j<10;j++) k = i+j;
}

int I2C_failed(void)
{
 i2c_stop();
 i2c_start3;

 SCCB_SCL_INPUT;
 SCCB_SDA_INPUT;

 return 0;
}

int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data )
{
 int i;

 i2c_start(i2c_start1);

 i2c_writeSlave(id);

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(addr)

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(data);

 i2c_end();

 return 1;
}

int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData ) 
{
 int i;
 unsigned char temp;

 i2c_start(i2c_start1);

 i2c_writeSlave(id);

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(addr)

 i2c_start(i2c_start2);

 // Write Slave ID
 id |= 1;
 i2c_writeSlave(id);

 // Read Data
 SCCB_SCL_LOW;
 temp = 0;
 for( i=7; i>=0; i-- )
 {
  SCCB_DELAY;
  SCCB_SCL_HIGH;
  if( SCCB_SDA_DATA )	 temp |= (1<<i);
  else							temp |= (0<<i);
  SCCB_DELAY;
  SCCB_SCL_LOW;
 }
 SCCB_SDA_HIGH;		  // No ACK
 SCCB_SDA_OUTPUT;
 SCCB_DELAY;
 SCCB_SCL_HIGH;
 SCCB_DELAY;

 i2c_stop();

 *pData = temp;

 return 1;
}

#endif

/* our IOCTLs consts */
#define MINIMAL_I2C_WRITE			0x0
#define MINIMAL_I2C_READ			 0x1
#define MINIMAL_MMU_FLUSHCACHE	   0x2
#define MINIMAL_MMU_INSTALLHACK	  0x3
#define MINIMAL_MMU_INSTALLHACK_32   0x4
#define MINIMAL_MMU_INSTALLHACK_48   0x5
#define MINIMAL_MMU_UNINSTALLHACK	0x6
#define MINIMAL_MMU_R001			 0x100
#define MINIMAL_MMU_R100			 0x101
#define MINIMAL_MMU_W100			 0x102
#define MINIMAL_MMU_R200			 0x103
#define MINIMAL_MMU_W200			 0x104
#define MINIMAL_MMU_R300			 0x105
#define MINIMAL_MMU_W300			 0x106
#define MINIMAL_MMU_R500			 0x107
#define MINIMAL_MMU_W500			 0x108
#define MINIMAL_MMU_R501			 0x109
#define MINIMAL_MMU_W501			 0x10a
#define MINIMAL_MMU_R600			 0x10b
#define MINIMAL_MMU_W600			 0x10c
#define MINIMAL_MMU_W750			 0x10d
#define MINIMAL_MMU_W760			 0x10e
#define MINIMAL_MMU_W770			 0x10f
#define MINIMAL_MMU_W751			 0x110
#define MINIMAL_MMU_W7131			0x111
#define MINIMAL_MMU_W761			 0x112
#define MINIMAL_MMU_W7101			0x113
#define MINIMAL_MMU_W7141			0x114
#define MINIMAL_MMU_W7102			0x115
#define MINIMAL_MMU_W7104			0x116
#define MINIMAL_MMU_W7142			0x117
#define MINIMAL_MMU_W704			 0x118
#define MINIMAL_MMU_W870			 0x119
#define MINIMAL_MMU_W850			 0x11a
#define MINIMAL_MMU_W851			 0x11b
#define MINIMAL_MMU_W860			 0x11c
#define MINIMAL_MMU_W861			 0x11d
#define MINIMAL_MMU_R900			 0x11e
#define MINIMAL_MMU_W900			 0x11f
#define MINIMAL_MMU_R901			 0x120
#define MINIMAL_MMU_W901			 0x121
#define MINIMAL_MMU_R1000			0x122
#define MINIMAL_MMU_W1000			0x123
#define MINIMAL_MMU_R1001			0x124
#define MINIMAL_MMU_W1001			0x125
#define MINIMAL_MMU_R1300			0x126
#define MINIMAL_MMU_W1300			0x127
#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mov	r0, %0\n\t" \
	"mcr	p15, 0, r0, " act "\n\t" \
	"ldmia sp!, {r0}\n\t": "=r" (arg)); }

#define MMU_READ(act,rt) \
{ asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mrc p15, 0, r0, " act "\n\t" \
	"mov %0, r0\n\t" \
	"ldmia sp!, {r0}\n\t": "=r"(rt)); }



static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
 return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
 return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{
int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); }
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); }

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));

CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg));
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg));

if(cmd == MINIMAL_MMU_FLUSHCACHE)
{
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
  return 1;
}

if(cmd == MINIMAL_I2C_WRITE)
{
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
}

if(cmd == MINIMAL_I2C_READ)
{
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK_32)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xff00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK_48)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xff00000f) == 0x03000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xfe00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_UNINSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xfe00000f) == 0x02000002 ) 
	   cpt[j] &= ~0xFFC; // TESTME: unset C and B bits in upper 32MB memory area... (right?)

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

 return -EINVAL;
}

static struct file_operations minimal_fops =
{
 owner:		  THIS_MODULE,
 ioctl:		  minimal_ioctl,
 open:		   minimal_open,
 release:		minimal_release,
};

static struct miscdevice minimal =
{
 255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
 misc_register(&minimal);
 return 0;
}

static void __exit minimal_exit(void)
{
 misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");
 
GnoStiC posted on Nov 22 2006 said:
http://gnostic.lryiu.com/gp2x/minimmu.rar

minimmu.o2 is structure-size-boundary=8 version

rlyeh posted on Nov 22 2006 said:
Got another source to compile :p
Thanks in advance
Click to expand...
Click to expand...

damn, no errors? i would not expect that from a source of mine :D

try this one too :)

Code: 
/* Kernel device driver for Minimal Library SDK. v0.2
   Based on previous work by Squidge and NK.
   Written by rlyeh, (c) 2006. */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/delay.h>
#include <asm/memory.h>
#include <asm/uaccess.h>

#if __GNUC__ == 3
#include <linux/version.h>
static const char __module_kernel_version_gcc3[] __attribute__((__used__)) __attribute__((section(".modinfo"))) =
"kernel_version=" UTS_RELEASE;
#endif


/* declarations for I2C IOCTLs */
#if 1

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/miscdevice.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/delay.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

extern int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
extern int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

typedef struct { unsigned char id,addr,data;} i2cw;
typedef struct { unsigned char id,addr,*pdata;} i2cr;


#define SCCB_SCL_INPUT	set_gpio_ctrl(GPIO_SCL, GPIOMD_IN, GPIOPU_NOSET)
#define SCCB_SCL_OUTPUT	set_gpio_ctrl(GPIO_SCL, GPIOMD_OUT, GPIOPU_NOSET)
#define SCCB_SCL_LOW	write_gpio_bit(GPIO_SCL, 0)
#define SCCB_SCL_HIGH	write_gpio_bit(GPIO_SCL, 1)
#define SCCB_SCL_DATA	read_gpio_bit(GPIO_SCL)

#define SCCB_SDA_INPUT	set_gpio_ctrl(GPIO_SDA, GPIOMD_IN, GPIOPU_NOSET)
#define SCCB_SDA_OUTPUT	set_gpio_ctrl(GPIO_SDA, GPIOMD_OUT, GPIOPU_NOSET)
#define SCCB_SDA_LOW	write_gpio_bit(GPIO_SDA, 0)
#define SCCB_SDA_HIGH	write_gpio_bit(GPIO_SDA, 1)
#define SCCB_SDA_DATA	read_gpio_bit(GPIO_SDA)

#define SCCB_DELAY	I2C_delay()


#define i2c_stop() {SCCB_SCL_LOW; SCCB_SDA_LOW;}

#define i2c_start1 {SCCB_SDA_HIGH; SCCB_SCL_HIGH; SCCB_SCL_OUTPUT; SCCB_SDA_OUTPUT; SCCB_DELAY; i2c_stop();}
#define i2c_start2 {i2c_stop(); SCCB_SDA_OUTPUT;}
#define i2c_start3 {SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SDA_HIGH;}

#define i2c_start(x) {{ x } \
		i2c_start3; \
	SCCB_DELAY; SCCB_DELAY; SCCB_DELAY; \
	SCCB_SDA_LOW; SCCB_DELAY; SCCB_SCL_LOW;}

#define i2c_writeSlave(what) \
	{for( i=7; i>=0; i-- ) \
	{ if( (what) & (1<<i) ) SCCB_SDA_HIGH; else SCCB_SDA_LOW; \
	  SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SCL_LOW; } \
	SCCB_SDA_INPUT; \
	SCCB_DELAY; \
	SCCB_SCL_HIGH; \
	if( SCCB_SDA_DATA ) I2C_failed(); \
	SCCB_DELAY;}

#define i2c_end() \
	{i2c_stop(); SCCB_DELAY; SCCB_SCL_HIGH; SCCB_DELAY; SCCB_SDA_HIGH; \
	SCCB_SCL_INPUT; SCCB_SDA_INPUT;}

int i2c_set;

int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data );
int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData );

void I2C_delay( void )
{
 volatile int i, j, k;
 for(i=0;i<20;i++) for(j=0;j<10;j++) k = i+j;
}

int I2C_failed(void)
{
 i2c_stop();
 i2c_start3;

 SCCB_SCL_INPUT;
 SCCB_SDA_INPUT;

 return 0;
}

int I2C_wbyte( unsigned char id, unsigned char addr, unsigned char data )
{
 int i;

 i2c_start(i2c_start1);

 i2c_writeSlave(id);

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(addr)

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(data);

 i2c_end();

 return 1;
}

int I2C_rbyte( unsigned char id, unsigned char addr, unsigned char *pData ) 
{
 int i;
 unsigned char temp;

 i2c_start(i2c_start1);

 i2c_writeSlave(id);

 SCCB_SCL_LOW; 
 SCCB_SDA_OUTPUT; 
 i2c_writeSlave(addr)

 i2c_start(i2c_start2);

 // Write Slave ID
 id |= 1;
 i2c_writeSlave(id);

 // Read Data
 SCCB_SCL_LOW;
 temp = 0;
 for( i=7; i>=0; i-- )
 {
  SCCB_DELAY;
  SCCB_SCL_HIGH;
  if( SCCB_SDA_DATA )	 temp |= (1<<i);
  else							temp |= (0<<i);
  SCCB_DELAY;
  SCCB_SCL_LOW;
 }
 SCCB_SDA_HIGH;		  // No ACK
 SCCB_SDA_OUTPUT;
 SCCB_DELAY;
 SCCB_SCL_HIGH;
 SCCB_DELAY;

 i2c_stop();

 *pData = temp;

 return 1;
}





#endif

/* our IOCTLs consts */
#define MINIMAL_I2C_WRITE			0x0
#define MINIMAL_I2C_READ			 0x1
#define MINIMAL_MMU_FLUSHCACHE	   0x2
#define MINIMAL_MMU_INSTALLHACK	  0x3
#define MINIMAL_MMU_INSTALLHACK_32   0x4
#define MINIMAL_MMU_INSTALLHACK_48   0x5
#define MINIMAL_MMU_UNINSTALLHACK	0x6
#define MINIMAL_MMU_R001			 0x100
#define MINIMAL_MMU_R100			 0x101
#define MINIMAL_MMU_W100			 0x102
#define MINIMAL_MMU_R200			 0x103
#define MINIMAL_MMU_W200			 0x104
#define MINIMAL_MMU_R300			 0x105
#define MINIMAL_MMU_W300			 0x106
#define MINIMAL_MMU_R500			 0x107
#define MINIMAL_MMU_W500			 0x108
#define MINIMAL_MMU_R501			 0x109
#define MINIMAL_MMU_W501			 0x10a
#define MINIMAL_MMU_R600			 0x10b
#define MINIMAL_MMU_W600			 0x10c
#define MINIMAL_MMU_W750			 0x10d
#define MINIMAL_MMU_W760			 0x10e
#define MINIMAL_MMU_W770			 0x10f
#define MINIMAL_MMU_W751			 0x110
#define MINIMAL_MMU_W7131			0x111
#define MINIMAL_MMU_W761			 0x112
#define MINIMAL_MMU_W7101			0x113
#define MINIMAL_MMU_W7141			0x114
#define MINIMAL_MMU_W7102			0x115
#define MINIMAL_MMU_W7104			0x116
#define MINIMAL_MMU_W7142			0x117
#define MINIMAL_MMU_W704			 0x118
#define MINIMAL_MMU_W870			 0x119
#define MINIMAL_MMU_W850			 0x11a
#define MINIMAL_MMU_W851			 0x11b
#define MINIMAL_MMU_W860			 0x11c
#define MINIMAL_MMU_W861			 0x11d
#define MINIMAL_MMU_R900			 0x11e
#define MINIMAL_MMU_W900			 0x11f
#define MINIMAL_MMU_R901			 0x120
#define MINIMAL_MMU_W901			 0x121
#define MINIMAL_MMU_R1000			0x122
#define MINIMAL_MMU_W1000			0x123
#define MINIMAL_MMU_R1001			0x124
#define MINIMAL_MMU_W1001			0x125
#define MINIMAL_MMU_R1300			0x126
#define MINIMAL_MMU_W1300			0x127
#define MINIMAL_MMU_DRAINWRITEBUFFER MINIMAL_MMU_W7104
#define MINIMAL_MMU_INVALIDATEICACHE MINIMAL_MMU_W750
#define MINIMAL_MMU_INVALIDATEDCACHE MINIMAL_MMU_W760

#define MMU_WRITE(act,ag) \
{ arg = ag; asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mov	r0, %0\n\t" \
	"mcr	p15, 0, r0, " act "\n\t" \
	"ldmia sp!, {r0}\n\t": "=r" (arg)); }

#define MMU_READ(act,rt) \
{ asm volatile( \
	"stmdb sp!, {r0}\n\t" \
	"mrc p15, 0, r0, " act "\n\t" \
	"mov %0, r0\n\t" \
	"ldmia sp!, {r0}\n\t": "=r"(rt)); }



static ssize_t minimal_open(struct inode *inode, struct file *filp)
{
 return 0;
}

static int minimal_release(struct inode *inode, struct file *file)
{
 return 0;
}

static int minimal_ioctl(struct inode *inode, struct file *file,
					 unsigned int cmd, unsigned long argm)
{
int ret, arg;

#define CMDR(c, a) if(cmd == (c)) { {a}; return (ret); }
#define CMDW(c, a) if(cmd == (c)) { copy_from_user(&arg, (int *)argm, sizeof(int)); {a}; return (1); }

//this group is here due to optimization reasons (faster execution)
CMDW(MINIMAL_MMU_W7104, MMU_WRITE("c7,c10,4",arg));
CMDW(MINIMAL_MMU_W750,  MMU_WRITE("c7,c5,0", arg));
CMDW(MINIMAL_MMU_W760,  MMU_WRITE("c7,c6,0", arg));
CMDW(MINIMAL_MMU_W770,  MMU_WRITE("c7,c7,0", arg));
CMDW(MINIMAL_MMU_W751,  MMU_WRITE("c7,c5,1", arg));
CMDW(MINIMAL_MMU_W7131, MMU_WRITE("c7,c13,1",arg));
CMDW(MINIMAL_MMU_W761,  MMU_WRITE("c7,c6,1", arg));
CMDW(MINIMAL_MMU_W7101, MMU_WRITE("c7,c10,1",arg));
CMDW(MINIMAL_MMU_W7141, MMU_WRITE("c7,c14,1",arg));
CMDW(MINIMAL_MMU_W7102, MMU_WRITE("c7,c10,2",arg));
CMDW(MINIMAL_MMU_W7142, MMU_WRITE("c7,c14,2",arg));
CMDW(MINIMAL_MMU_W704,  MMU_WRITE("c7,c0,4", arg));

CMDR(MINIMAL_MMU_R001,  MMU_READ("c0,c0,1",  ret));

CMDR(MINIMAL_MMU_R100,  MMU_READ("c1,c0,0",  ret));
CMDW(MINIMAL_MMU_W100,  MMU_WRITE("c1,c0,0", arg));
CMDR(MINIMAL_MMU_R200,  MMU_READ("c2,c0,0",  ret));
CMDW(MINIMAL_MMU_W200,  MMU_WRITE("c2,c0,0", arg));
CMDR(MINIMAL_MMU_R300,  MMU_READ("c3,c0,0",  ret));
CMDW(MINIMAL_MMU_W300,  MMU_WRITE("c3,c0,0", arg));
CMDR(MINIMAL_MMU_R500,  MMU_READ("c5,c0,0",  ret));
CMDW(MINIMAL_MMU_W500,  MMU_WRITE("c5,c0,0", arg));
CMDR(MINIMAL_MMU_R501,  MMU_READ("c5,c0,1",  ret));
CMDW(MINIMAL_MMU_W501,  MMU_WRITE("c5,c0,1", arg));
CMDR(MINIMAL_MMU_R600,  MMU_READ("c6,c0,0",  ret));
CMDW(MINIMAL_MMU_W600,  MMU_WRITE("c6,c0,0", arg));

CMDW(MINIMAL_MMU_W870,  MMU_WRITE("c8,c7,0", arg));
CMDW(MINIMAL_MMU_W850,  MMU_WRITE("c8,c5,0", arg));
CMDW(MINIMAL_MMU_W851,  MMU_WRITE("c8,c5,1", arg));
CMDW(MINIMAL_MMU_W860,  MMU_WRITE("c8,c6,0", arg));
CMDW(MINIMAL_MMU_W861,  MMU_WRITE("c8,c6,1", arg));

CMDR(MINIMAL_MMU_R900,  MMU_READ("c9,c0,0",  ret));
CMDW(MINIMAL_MMU_W900,  MMU_WRITE("c9,c0,0", arg));
CMDR(MINIMAL_MMU_R901,  MMU_READ("c9,c0,1",  ret));
CMDW(MINIMAL_MMU_W901,  MMU_WRITE("c9,c0,1", arg));

CMDR(MINIMAL_MMU_R1000, MMU_READ("c10,c0,0", ret));
CMDW(MINIMAL_MMU_W1000, MMU_WRITE("c10,c0,0",arg));
CMDR(MINIMAL_MMU_R1001, MMU_READ("c10,c0,1", ret));
CMDW(MINIMAL_MMU_W1001, MMU_WRITE("c10,c0,1",arg));

CMDR(MINIMAL_MMU_R1300, MMU_READ("c13,c0,0", ret));
CMDW(MINIMAL_MMU_W1300, MMU_WRITE("c13,c0,0",arg));

if(cmd == MINIMAL_MMU_FLUSHCACHE)
{
  asm volatile (".word 0xef9f0002"); // swi #0x9f0002
  return 1;
}

if(cmd == MINIMAL_I2C_WRITE)
{
  i2cw i2c_write_info;

  if(copy_from_user(&i2c_write_info, (i2cw *)argm, sizeof(i2cw)))
   return -EFAULT;

  mdelay(1);
  I2C_wbyte(i2c_write_info.id, i2c_write_info.addr, i2c_write_info.data);
  return 1;
}

if(cmd == MINIMAL_I2C_READ)
{
  i2cr i2c_read_info;

  if(copy_from_user(&i2c_read_info, (i2cr *)argm, sizeof(i2cr)))
   return -EFAULT;

  I2C_rbyte(i2c_read_info.id, i2c_read_info.addr, i2c_read_info.pdata);
  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK_32)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( (cpt[j] & 0xff00000f) == 0x02000002 ) 
	   cpt[j] |= 0xFFC; // set C and B bits in 32-48MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK_48)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( ((cpt[j] & 0xff00000f) == 0x03000002)
	 && ((cpt[j] & 0xffff0000) != 0x03FF0000) /*avoid caching our reserved area (dualcore+940t stack)*/
	 )
	   cpt[j] |= 0xFFC; // set C and B bits in upper 48-64MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_INSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( ((cpt[j] & 0xfe00000f) == 0x02000002) 
	 && ((cpt[j] & 0xffff0000) != 0x03FF0000) /*avoid caching our reserved area (dualcore+940t stack)*/
	 )
	   cpt[j] |= 0xFFC; // set C and B bits in upper 32-64MB memory area...

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

if(cmd == MINIMAL_MMU_UNINSTALLHACK)
{
  unsigned int *pgtable, *cpt;
  int i,j,ttb;

  // get the pointer to the translation table base...
  MMU_READ("c2,c0,0", ttb);

  for (pgtable = __va(ttb), i = 0; i < 4096; i ++)
   if ( (pgtable[i] & 3) == 1 ) 
	for (cpt = __va(pgtable[i] & 0xfffffc00), j = 0; j < 256; j ++)
	 if ( ((cpt[j] & 0xfe00000f) == 0x02000002) )
	   cpt[j] &= ~0xFFC; // TESTME: unset C and B bits in upper 32MB memory area... (right?)

  // drain the write buffer and flush the tlb caches...
  MMU_WRITE("c7,c10,4",0)
  MMU_WRITE("c8,c7,0",0);

  return 1;
}

 return -EINVAL;
}

static struct file_operations minimal_fops =
{
 owner:		  THIS_MODULE,
 ioctl:		  minimal_ioctl,
 open:		   minimal_open,
 release:		minimal_release,
};

static struct miscdevice minimal =
{
 255, "minimal", &minimal_fops
};

static int __init minimal_init(void)
{
 misc_register(&minimal);
 return 0;
}

static void __exit minimal_exit(void)
{
 misc_deregister(&minimal);
}

module_init(minimal_init);
module_exit(minimal_exit);

MODULE_AUTHOR("rlyeh / www.retrodev.info");
 
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