I'm trying to do cachegrind profiling, but valgrind cannot auto-detect the cache config, so I'll have to set it manually. Can someone help me with that? According to the TI website (http://www.ti.com/product/omap3530#technicaldocuments), the size of the L1 cache is 32KB and the L2 cache is 256KB, but it doesn't say how it is divided between instruction and data cache, what the line sizes are, etc.
So in other words, I would like to know what options to give to cachegrind:
--I1=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the level 1 instruction cache.
--D1=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the level 1 data cache.
--LL=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the last-level cache.
I don't even know what units these command-line arguments expect (bytes? words?).
So in other words, I would like to know what options to give to cachegrind:
--I1=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the level 1 instruction cache.
--D1=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the level 1 data cache.
--LL=<size>,<associativity>,<line size>
Specify the size, associativity and line size of the last-level cache.
I don't even know what units these command-line arguments expect (bytes? words?).