I must keep replying to closed threads. Anyway, in an isr to handle vsync interrupts do you need to set bit 2 of the DPC_INTR register in the isr? The example in a previous thread on this did not.
Counting interrupts I get about 111 per second. In theory that means 111 frames per second if you can create and move data that fast.
A fast memcpy from cached ram to the video page can copy 116 pages per second. Using LDM/STM pairs 4 words (16 bytes) at a time. This is on the 940.
And if I have my math right that leaves 77,000 clock cycles to draw something (200mhz). There are 76,800 pixels so you cannot draw or change every one, but you could change some of them each frame.
Do these numbers sound reasonable/correct?
Counting interrupts I get about 111 per second. In theory that means 111 frames per second if you can create and move data that fast.
A fast memcpy from cached ram to the video page can copy 116 pages per second. Using LDM/STM pairs 4 words (16 bytes) at a time. This is on the 940.
And if I have my math right that leaves 77,000 clock cycles to draw something (200mhz). There are 76,800 pixels so you cannot draw or change every one, but you could change some of them each frame.
Do these numbers sound reasonable/correct?