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While not ideal, all GLES2 devices support ETC1 I believe. Obviously sometimes it will do better than PVRTC (and sometimes worse), but it might be worth using that as a standard compression format if it's a GLES2 capable device, and using PVRTC if it's not. To be honest, I fear that supporting...

That's not even including the two co-processors, which each run at 150Mhz and can do 4 FMACs per clock. (For comparison, the Cortex can do 2 FMACs/clock with more latency) And the monstrous fillrate of 1200 texel/s (versus about 300 or so for the SGX even including overdraw) or the fact that...

To avoid bumping the main thread, as it is a bit dated... Isn't there an extension to upload non-swizzled textures? Might this improve things somewhat? GL_Img_Texture_Stream I believe it is (PowerVR newsletter #11) Not read up about it other than the fact that it exists. I have no idea if...

Hrm, a fair point. It implies that is is pipelined, but as you say, it says So the question is, is that 7 cycles blocking the next operation, or 7 cycles pipelined, but unforwardable. I can't see it mentioning forwarding if it doesn't apply. That said, it should be easy to check - if you...

Why not just switch (optionally) into runfast mode. It won't be as quick as NEON, but it will give you semi-pipelined floating point, as long as it is actually pipelinable. (if you had 9 independant multiply-adds they will run pipelined). This is a fairly togglable setting I would have thought...

Are you sure that VMUL + VMLA is a special case for floats? I think it is for integers, but for floats there is still a latency. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344j/ch16s06s03.html Is the integer one, and it says But the float one says no such thing, instead...

The downside of this is the huge latency though surely - VMLA has about an 8 cycle latency or something mad. And I thought NEON could do single cycle "simple" swizzles in the LS unit, with complex rearrangements taking 4 cycles - although obviously the scheduling might be tricky - if you were...

Other things I read show it as being the 520 rather than the 535, although I don't think anybody is that sure. the 5*5 I think have a SIMD unit rather than scalar units, I think that might be overkill in a mobile device. I don't think anybody is 100% sure exactly which SGX it is using, however...

I think that handling mixed 16/32 bit instructions, while not as "nice" as plain word-aligned 32bit instructions is not that evil anyway - I think when you go superscalar you would want to be able to handle two instructions straddling a cache-line by pre-fetching (or whatever), in which case you...

I thought the primary aim of supporting both was that Thumb2 is the desired future path for ARM (this seems to be the implication from the fact that certain things are now supported ONLY in T2, such as NEON predication), but for an app processor there is a significant advantage in offering both...

Interesting... is the errata list available? Seems a bit of a pain. Of course, if we don't use Thumb-2 then NEON ops can't be predicated, although that's not exactly the worst thing in the world.

What about the IT instruction? http://infocenter.arm.com/help/topic/com.arm.doc.dui0204i/Cjabicci.html My understanding was that this was used instead of predicate bits in the instruction itself.

I thought they could be predicated based upon the ARM flags? The documentation seems to imply this is the case, at least in Thumb2. The (somewhat sick) approach I was suggesting earlier was attempting to abuse permute to achieve "simulated" predication in NEON, although obviously at a higher...

Sorry for the extra post - my reading of the ARM docs indicates this is only where there is a destination hazard - if you have an IF and the ELSE part right next to each other "Instructions with the same destination cannot be issued in the same cycle. This can happen with conditional code."...

I'm tired, so obviously this doesn't make perfect sense - but the gist should be there at least! (you do do an inverted comparison if the instruction does insert -1 when it matches, and then you OR - but if it worked as I described you would do a straightforward comparison - but reading it...

Well, I'm not an assembly programmer, so you might want to check that I am sane. So, my idea is that VTBX takes an array looking something like [0,1,2,3,4,5,6,7] and then will select the 0th byte, etc upwards of the target. (Obviously for a q register it would go up to 15). So if you wanted...

Predicate execution is dependant upon the ARM bits from my reading, and predicated instructions are squashed before they hit NEON. Of course, not a CPU designer, so I may have understood wrong. The NEON bit has arbitary permute and comparison functions, so you can simulate predication on NEON by...

Not an expert - but can't you use the VTBL/VTBX instructions to avoid branches? It obviously depends exactly what you are trying to do - and it won't work if the aim is not to write anything at all, but if the choice is "pick A if <0 or B otherwise", then I think you can do it all in NEON...

It requires specially written VMs for Jazelle - either form. http://people.ubuntu.com/~doko/java/openjdk6-armel/ the JDK is available, although it would appear that there is no JIT support in it at the moment for ARM. However I imagine it would not be impossible to add, and there are...

Assuming a dot product is a1*b1+a2*b2+a3+b3+a4*b4 Then my reading of the instruction cycle timings would be that you would take 4 cycles, but you could do two of them in that time. (assuming MUL, then MAC, MAC, MAC). My reading of the NEON stuff is that it pretty much can only do two floating...