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Yes, that's the bug. If it happened often, I think I would have noticed. It's probably only noticable in certain cases. I'll look into it. I see what I did. Wow, that was a really stupid bug. I converted add zero to mov (or nothing) but not xor. hmm.. I guess I need to benchmark this...

It does handle the link register (in sjump_assemble) like so: return_address=start+i*4+8; emit_movimm(return_address,rt); // PC into link register The unfinished part is where the delay slot can not be reordered due to a dependency. Fixing this is probably as simple as copying...

There were 9 places where you reversed the endianness, and most of the rest was removing FPU, 64-bit, and TLB. I thought changing the memory layout would be more complex, though from what you say, this might need more work. I'm fairly certain no N64 games rely on this behavior for JALR...

I'd like to know what recompiler you think has a good design. :) Every CPU core that I've ever seen has either code duplication or an excessive number of macros that make the code unreadable. It's kinda inevitable when you have many instructions with similar but not identical operations. I...

It's not so much Java that's the problem, but that native code has to be loaded as a shared library. This memory layout makes allocating memory for the dynarec somewhat complicated. For a good laugh, read the thread on emutalk.net about this. WTF? If that instruction doesn't work on the...

What Intel does is to fuse a compare+branch into a single macro-op. This then goes into the reorder buffer and can be issued early if there are no dependencies. I don't know what it's actually doing, I just remember seeing the odd glitches. It's very noticable in OoT where you can walk right...

What's this all about?

I'm not sure exactly what the bottleneck is, but the OMAP3530 is using many more cycles than the number of instructions executed. The branch misprediction penalty can be reduced by resolving the branch early. I don't know if A9 is capable of that, but other chips do this (eg PowerPC). The...

I can confirm that unconditional branches do not get GHB entries. I was unable to create GHB collisions between conditional branches and unconditional branches, as occurs between two conditional branches. So the unconditional branches do seem to be flagged in the BTB. It also seems to...

Assuming you're referring to the TLB-related split block bug, which affected both of these games, that was fixed in 20101026. Conker's Bad Fur Day runs very slow, and is unplayable due to lack of graphics rendering. Perfect Dark should be okay. Make sure you enable the memory expansion.

The TRM suggests that the pipeline is restarted on a cache miss, so it's likely that the fetch is stopped... I just hadn't thought about it before. I was able to consistently cause branch mispredictions with the following: mov r0,#16777216 loop: (some not-taken branches) teq r0,r0 beq .+4...

I haven't seen any direct evidence that the fetch is stalled during d-cache misses. It's possible though. How did you determine this? There's a catch to aligning branches. The GHB is indexed by the low bits of the instruction address. If you put all branches at the end of a 64-bit block...

The issue that I ran into with the loads dual-issuing with branches was code like the following b target ldr r0,[r1]If the branch has not been seen before, it will have no entry in the BTB and will be predicted not-taken. This pair of instructions can dual-issue, and since the memory load...

Every graphics chipset has different performance limitations and driver bugs. It doesn't matter what you use for development, if your intent is to make a cross-platform game, you have to test on a wide variety of hardware.

Branches issue at a rate of one per cycle. The stall occurs in instruction fetch when a branch is predicted taken. There is a one-cycle delay before the target address from the branch predictor is passed to the L1 cache. Since the instruction decoder maintains a queue, if the pipeline is...

Well, it's about as plausible as N64 emulators coming from a 14-year-old kid, or some guy's imaginary friend named Rolf. And quite a few people actually believed that...

The recompiler is pretty efficient. It might be possible to do some sort of HLE, but I don't have any really good ideas. A lot of the time is spent waiting for the L2 cache. Higher clock speed is helpful if it speeds up the cache. OoOE might help if the processor can do something else while...

Your bizarre stuff has inspired more than one member's title :)

If you need 512MB RAM, there's the touchbook from Always Innovating. If it doesn't have to be a laptop, you can use a Beagleboard-XM, which also has 512MB.

They're probably using ffmpeg as on the A320. There is no way a 600MHz ARM11 can decode 1080p H.264.