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I found a couple small inefficiencies, but it's probably only around 1% or 2% speedup.

You mean this one? I'll try to post an updated version in the next few weeks. Most of the fixes are rare problems that don't affect most games.

I got some bug reports that I'm looking into. I have fixes for most of these issues, but I need to test some more games to make sure they work.

If you want to handle this in the dynamic recompiler, pagespan_ds() generates code that executes one instruction and then branches. This is invoked by calling new_recompile_block(address+1). Put the branch target address in r8 (or whatever HOST_BTREG is) and then jump to the block that it...

Yes; it looked like you only patched the second case.

Supposedly there are additional pins. http://news.cnet.com/8301-30685_3-20027455-264.html

Some time ago I marked several pages with [Category:Spam]. They eventually got deleted.

Oh wait... there's more. I think this fixes all the cases: --- r4300/new_dynarec/new_dynarec.c.old 2011-01-09 22:25:01.777969039 -0500 +++ r4300/new_dynarec/new_dynarec.c 2011-01-15 16:52:27.735747033 -0500 @@ -9358,13 +9361,35 @@ f_regmap[hr]=regs[i].regmap[hr]...

If the address is between 0x000000 and 0x1FFFFF then the carry flag will be clear. If it's between 0x80000000 and 801FFFFF then the overflow flag will be set. We don't care about the carry flag. :)

I think that's it. The other case is below (comment says "no-match due to different register") and that one is handled correctly. The code is kinda messy, but basically it starts at the branch instruction, looks at the history, then searches forward from the branch target. If the registers...

The register allocation is clearly screwed up here. Let me look into it some more. Be careful with this - if you disable the liveness analysis, you also need to turn off constant propagation as it relies on this data for certain edge cases. Doing this does generate less efficient code, around...

To clarify the MTC0 12 situation in case it is not clear... Basically this is the MIPS instruction which enables/disables interrupts. If an interrupt comes in while interrupts are disabled, then it waits until interrupts are enabled again, and then the interrupt is taken. Mupen64plus handles...

That's fine. That assert realy didn't need to be there. It was just there to catch junk that might not be real code. The catch here is that MTC0 12 can trigger an interrupt. The assert was there because I didn't implement the code to figure out what the correct return address was if the...

I've looked over the code and all the ALU instructions seem to be correct, but it looks like r0 can get written in MFC0, and also in your cop2 functions. This is easy to fix. By the way, what is going on with r6 in the above example? It gets written twice. I don't recall seeing that bug...

Whoops. Most instructions get ignored if they write r0 (ie: if(rt1[i])...) but I figured that loads needed to check for pagefaults and I/O. I guess I forgot to skip the actual load. I don't think I missed any other cases, but I'll double-check. BTW I suppose it would be possible to get rid...

I assumed that is the case, but didn't test it on real hardware. In the emulator, I update RA after the delay slot, which might not be accurate if the delay slot instruction modifies RA. I believe both branches are taken. The first branch is taken, one instruction is executed from its target...

I hope you don't find any; accurately emulating load delay slots in a dynamic recompiler is quite a complex task.

Nope... My code does not emulate load delay slots, and I don't see any changes related to this in Notaz's port. Also I don't know what is supposed to happen if you execute a JAL or BGEZAL instruction and access the link register in the delay slot, nor did I try to handle branches in the branch...

I can confirm that this is an actual bug. It occurs (theoretically) when the register allocator uses a temporary register to hold the register used for address generation in a SWR or SWL instruction. This will only occur if no other nearby instructions use the same register. Since SWL...

This works for me... --- ../Mupen64Plus-1-5-src-arm-20101026/r4300/new_dynarec/new_dynarec.c 2010-10-26 12:50:30.000000000 -0400 +++ r4300/new_dynarec/new_dynarec.c 2010-12-28 15:38:17.202274651 -0500 @@ -3027,11 +3027,6 @@ } type=STORED_STUB; } - if(jaddr) { -...