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    Dreamcast Emu?

    This has been discussed many times. The clock frequency of the CPU is generally not the limiting factor. The ability to emulate Dreamcast is mainly dependent on the speed of the RAM, L1/L2 cache, FPU, GPU, and, for games that use virtual memory, how much overhead the TLB emulation incurs.
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    Cpu For Pandora 2 ?

    What the heck are you talking about?
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    Dreamcast would be awesome

    Yabause has a fairly complex method of detecting wait loops, although it won't handle procedure calls and jump tables. http://yabause.svn.sourceforge.net/viewvc/yabause/trunk/yabause/src/sh2idle.c?revision=2375&view=markup
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    Cortex A15 - 5x faster.

    They really need a 64-bit instruction set if they want to get into this market. I don't think PAE hacks are going to cut it.
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    Dreamcast would be awesome

    Looking at the source code of nulldc, it does appear to do something reasonable with the SLEEP instruction. I would've asked, but his blog is closed to comments.
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    Dreamcast would be awesome

    I don't know of any SNES emulators that do idle loop detection anyway. Snes9x treats WAI/STP as a busy wait loop. Yeah but even given that, his numbers don't make a lot of sense. He adds inline+static to come up with 27M instructions (81%). That doesn't seem right.
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    Dreamcast would be awesome

    I'd expect that most would. Traditionally console games render at a fixed frame rate, halting the CPU and waiting for the next vblank interrupt. Games on modern hardware are less likely to be designed this way, but it was still fairly common in the late 90s. Not sure about the DS, but a lot...
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    Dreamcast would be awesome

    The SH4 has a SLEEP (idle) instruction. No idea how many games use it. So 3 bus cycles, plus 5 or 6 bus cycles (for 50ns or 60ns RAM) plus 3 bus cycles for the rest of the data transfer (cache line size is 32 bytes). The CPU can continue once the cache line is partially filled, so the...
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    Dreamcast would be awesome

    Almost all modern emulators have idle loop detection, I assume that's what drk||Raziel is doing. I doubt he's modelling the internal stalls and cache misses. If the Dreamcast RAM is really 64-bit and 100MHz as often claimed, the cache misses probably aren't that severe. 60ns DRAMs were pretty...
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    Dreamcast would be awesome

    http://drk.emudev.org/blog/?p=143 Interesting. He is claiming Dreamcast games execute 120-200 MIPS. 40% of that is movs and saveT, which can be combined with other instructions by the dynarec, but still that leaves around 100 million per second. That's about 5 times what N64 emulation...
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    What Does Optimized Even Mean?

    For WizardStan's example: mov $320,%eax mul y add x,%eax vs mov y,%eax lea (%eax,%eax,4),%eax shl $6,%eax add x,%eax Based on register availability, I might go with the latter. x86 mul is annoying since it needs EAX and EDX. My latest project is trying to optimize this function in...
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    Beta Mupen64Plus

    I have noticed that combining the plugins from the pnd with my local builds does not work. I don't know what Adventus did differently, but his binaries are not compatible. If you're going to do your own builds, make sure you compile everything from source.
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    Mupen64Plus

    The issue with Zelda (and Kirby) is a known regression in gles2n64, previously discussed here. I haven't tried to track down exactly which change broke it. (I was hoping Adventus would...)
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    Mupen64Plus

    It includes the register allocation fix which was the cause of crashes in Super Smash Bros. The other major fix was to ensure that things are deallocated in the proper order when freeing memory, as removing pointers in the wrong order led to crashes due to not detecting self-modifying code...
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    Beta Mupen64Plus

    Mostly I fixed crashes. For example, there was a bug where self-modifying code would go undetected during memory deallocation. It would work fine until the dynarec got low on memory and then crash randomly.
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    Mupen64Plus

    http://bunnitude.com/ari64/mupen64plus-arm-20100819.tar.gz Changes since 20100627: Fixed register allocation where a branch jumps into a delay slot of another branch Fixed TLB/COP0 register corruption Fixed self-modifying code detection during block deallocation Some fixes for cases where...
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    Pandora Lifetime

    I'm curious how much the larger L1 improves things too. OMAP3530 does actually spend quite a lot of time in L2 wait. I've also seen some issues with the write buffers getting full, which I assume is blocking on L1->L2 writeback.
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    Beta Mupen64Plus

    Known issue. http://code.google.com/p/mupen64plus/issues/detail?id=244
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    Beta Mupen64Plus

    I'll look into it at some point. Right now I'm still trying to track down some bugs in the dynamic recompiler.
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    Beta Snes9X4D4P - Another New Build, Now With Hi Res And New Rom Picker

    Secret of Mana and Seiken Densetsu 3 are high-res.
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