Search results

Welcome to the forum! Actually I was, yet I had managed to completely forget about that one! It has also been ported to a newer u-boot by rcn: https://github.com/RobertCNelson/Bootloader-Builder/blob/master/patches/ti-2015.07/0001-IGEPv5-Added-IGEPv5-board-support.patch I see absolutely...

Yo Tony! What brought you here? It does run in LPAE, but with 2GB still so far. The other half is still having a bit of a fight with the init since it's dual-rank, so not much examples around, and the ram init code in u-boot is... not very transparent, especially since TI is using undocumented...

More photo! More random info! (unrelated to above, snippet from a kernel startup) [ 0.156495] smp: Bringing up secondary CPUs ... [ 0.237729] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.238211] smp: Brought up 1 node, 2 CPUs [ 0.238226] SMP: Total of 2 processors...

For your documentation collection: :-) It should yes. One reason I've wired up the JTAG setup above is since it makes it easy to fiddle with memory config:

\o/ <zmatt> ok I typed \o/ in a forum post... what the HELL is that smiley it replaced it with <JonnyH> Some kind of eldritch horror that's 90% mouth? I don't know what the stackup is for the pyra cpu board, but the suggested stackup given in the omap5 datasheet is 10 layers, with blind and...

Extremely rarely I think, only as last resort. I can reflash the pyra if it gets hosed. This seems far more problematic for the modem. We both seem to be speculating however about the exact nature and purpose of EMERG_OFF and the risks of a power cut, and I agree the manual isn't really...

The manual states that after triggering emergency shutdown using EMERG_OFF, Please note that the power supply voltage (BATT+) may be disconnected resp. switched off only after having reached Shut Down as indicated by the PWR_IND signal going high. Since, as you mentioned, EMERG_OFF already...

I already did, you just couldn't compile it because your gcc was ancient

I currently have no reason to doubt it will work though, especially since the ipumm repository was discovered. It just requires some work be put in to make it actually work. That's actually completely trivial using drm.

... Ehm, no? If you want to waste a led on that feel free to configure that, I'll pass on an always-on led.

That's pretty clear yeah This is indeed a rare case where ??? is the appropriate punctuation since the first thing I said in my post was: Sigh, so now we have a power switch on the battery supply line to the module, ...

Sigh, so now we have a power switch on the battery supply line to the module, even though its documentation repeatedly warns not to disconnect this supply until the module has been powered down; the EMERG_OFF input it provides to forcibly power if off (if shutting it down cleanly is not an...

Wouldn't this design invite putting a lot of strain on the USB3 connector on the pyra due to its leverage? It could be avoided by giving the adapter a female USB3 B socket (normal or micro) and connect it via a cable, though it wouldn't make the overall assembly prettier I guess... Dibs on one...

OK, so I guess they do exist, although they're clearly non-standard, obscure, and are apparently just multi-chip packages meant for footprint reduction.

Eh, no, there are two 32-bit channels connecting to four 16-bit wide memory devices (32-bit wide ddr3 devices do not exist). In theory yes, but I think it would be quite expensive. (In case anyone wonders: yes, 8GB would be the final limit: larger dual-rank ddr3 memory devices do not exist...

Most relevant information can be found in the OMAP543x Technical Reference Manual, which you can download here, and don't forget to grab the errata while you're there. The main cpu is an ARM Cortex-A15 r2p0 (REVIDR=0) so you'll want to grab docs for that too: ARM v7-A/R Architecture Reference...

As far as I know the userspace libs need to be compiled for exactly the right core configuration and revision or they simply won't work.

times 1066 MT/s yields just under 8 GB/s of bandwidth, under ideal circumstances. The 4GB ram might have slightly worse bandwidth since I think it needs to insert a bus turnaround cycle when switching between ranks (at least when reading). On the other hand two ranks means 16 banks in total...

DDR3 allows the timing to be adjusted per byte lane in steps of a small fraction of a nanosecond, and the omap5 can perform this adjustment automatically (this is known as "hardware leveling"). Also the speed at which it runs (DDR3-1066, i.e. 533 MHz) is not very high compared to PCs. As...

That's however really not 2560x1600. :P That's... 1080p with a small flap stuck to its belly.