I finally got a free evening to try the GLSDK 6.03.00.01 "reference build" I did earlier this month, and I think I got the AESS working on Linux-3.8. I was playing back 44.1 kHz wav file with 98% idle (top), and I got these printouts in the kernel log:
[ 8571.756805] omap-dma-engine...
Earlier this week I set out to build the original TI SDK for the omap5 line of cards. I went with the GLSDK 6.03.00.01 release. That's the last one which lists official support for OMAP5. All the SKDs can be found here: https://software-dl.ti.com/dsps/dsps_public_sw/glsdk/index.html
The TI...
I tested out a timer and it did improve things, but I'm still able to reproduce the issue. I made some more changes and I believe I have a stable solution now:
if the calculated lower threshold level is below the configured minimum level, clamp the value to 0 and disable the threshold
change...
Yeah, my devboard always boots too. I haven't checked my power supply, but it could be that. I figure that overheat should show at least some warning in the logs before shutdown
Latest userspace changes pushed to https://github.com/Risca/pyra_vol_mon now. No timer added yet, but it's prepared for it. @hns, I applied some fixes for threshold handling that you made in the Lerux repos. I hope you approve :)
Please be aware that this was coded in the middle of the night...
Okay, I think I have something that should be much more stable now. Two commits:
https://github.com/Risca/linux/commit/307e3ef6941663ef7a179c7c5d98edee3e9c156d
https://github.com/Risca/linux/commit/28293e6b5497a3cff99605ed080a57a5a7c7789c
I'm working on some improvements to the userspace...
I think I've found the root cause of that bug: we both accept 0 as a valid threshold value and test thres != 0 to see if a channel is configured. Hence, if a threshold value is set to 0 we no longer detect the channel as configured :oops: I'm working on a fix now. Not sure which is best, though...
Has anyone checked if this errata bug is relevant for memory freezes?
i878 MPU Lockup With Concurrent DMM and EMIF Accesses
CRITICALITY High
DESCRIPTION The MPU has two primary paths to DDR and system address space via the MPU
Memory Adapter (MPU_MA).
The Low Latency path is the predominant...
Just a short heads up that I'm not gonna have time to work on this for at least a couple more days. Maybe not until after Christmas. Quite swamped with other commitments right now.
EDIT: I'm still gonna poll the forums looking for the latest updates :D
The userspace daemon has received a couple of nice fixes from another helpful netizen :D I've been too busy myself to work on this lately, so your work is very appreciated @hns
Hmm... I have a couple of ideas, but I'm quite busy this week. You could try the --min flag to clamp the minimum value to e.g. 10 or something.
I sometimes notice that the very first reading is slow/times out, but subsequent reads are much, much faster. How slow are we talking about here?
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