Hi Nikolaus, Good thinking, but I remember trying that in the last set of tests and no dice. I think the problem is noise on the clock from TWL to OMAP setting the PDM modulator out of kilter until it is reset, rather than just a phase issue.BestDavid
-------- Original message --------From: "H. Nikolaus Schaller" hns@goldelico.com Date: 19/10/2020 14:41 (GMT+00:00) To: David Shah dave@ds0.me Cc: Michael Mrozek EvilDragon@openpandora.org, kernel@pyra-handheld.com Subject: Re: TWL6040 decoupling Hi all,picking up this discussion on Michael's suggestion, I have looked again into the details of the problem.I noticed that there is the PDMCLK-Output which makes trouble depending on chip internal, external (wire length) and OMAP delays.This would verify that we really have the problem described as OMAP5 erratum i800 resp. twl6040 erratum 6 "PDM Downlink Data Corrupted".Now I found reference that the PDMCLK is either derived from MCLK (which is our 19.2 MHz master clock) or the 32kHz low-power clock.In any case the MCLK is 19.2 MHz and the PDMCLK is usually 19.2 MHz.If I look at the timing figure of the twl6040 erratum 8 there are less than 26ns available for all the delays of the buffers plus the pdm-clk.I wasn't aware that both directions count (twl -> OMAP and back) so the real margin is probably less than 10ns for the wiring on the PCB.This is roughly equivalent to 3cm distance between twl6040 and omap.Another finding is that if the PDMCLK is derived from 32kHz it can also be 17.64 MHz which would give some additional ns margin forthe signal delays and avoid the twl erratum.Is it possible to switch the twl6040 to run from 32kHz and use PDMCLK 17.64 MHz to check if it makes a difference?BR and thanks,Nikolaus